Silicon-on-insulator Lateral Insulated Gate Bipolar Transistor Research Articles

A novel low turnoff loss carrier stored SOI LIGBT with trench gate barrier

A novel low turnoff loss carrier stored (CS) silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) with trench gate barrier (CS SOI TGLIGBT) is proposed. The proposed CS SOI TGLIGBT features a trench gate inserted between the pwell and n-drift. Firstly, the trench gate acts as a hole barrier to prevent the hole from injecting directly into pwell in the on-state, which introduces carrier stored effect and realizes a uniform carriers distribution in the n-drift region, resulting in a decrease of the on-state voltage drop (Von). Secondly, due to the carrier stored effect and the assisted depleted effect induced by the trench gate, large number of carriers can be quickly removed at the initial turnoff process, leading to a decrease of turnoff loss (Eoff). The influences of gate trench barrier on Von and Eoff are investigated. Simulation results show that the proposed CS SOI TGLIGBT can achieve a 59% lower Eoff compared with the conventional SOI trench gate LIGBT at the same Von of 1.15 V.

The Hot-Carrier-Induced Degradation of SoI LIGBT Under AC Stress Conditions

The hot-carrier-induced degradation of silicon-on-insulator (SoI) lateral insulated gate bipolar transistor (LIGBT) under various ac stress conditions has been investigated. The gate voltage of the SoI LIGBT is pulsed with different frequencies, duty cycles, and rise/fall times, while a constant voltage is applied at the collector. Experiments show that the RON degradation is enhanced by increasing the gate pulse stress frequency. In addition, large duty cycle with fixed gate pulse stress frequency produces more severe RON degradation. Furthermore, the influence of the pulse rise/fall times on the RON degradation is also studied. It has been discovered that the short pulse rise/fall times imply much more serious hot-carrier degradation. Based on the experiments and simulations, several possible dynamic degradation mechanisms are proposed.

A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch

A high voltage (> 600 V) integrable silicon-on-insulator (SOI) trench-type lateral insulated gate bipolar transistor (LIGBT) with a reduced cell-pitch is proposed. The LIGBT features multiple trenches (MTs): two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX). Firstly, the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si. Secondly, oxide trenches bring in multi-directional depletion, leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field (RESURF) effect. Both increase the breakdown voltage (BV). Thirdly, oxide trenches fold the drift region around the oxide trenches, leading to a reduced cell-pitch. Finally, the oxide trenches enhance the conductivity modulation, resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop (Von). The oxide trenches cause a low anode—cathode capacitance, which increases the switching speed and reduces the turn-off energy loss (Eoff). The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm, a Von of 1.03 V at 100 A/cm−2, a turn-off time of 250 ns and Eoff of 4.1×10−3 mJ. The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits, simplifying the fabrication processes.

Modeling Voltage Derivative During Inductive Turnoff in Thin SOI LIGBT

The lateral insulated gate bipolar transistor (IGBT) behavior differs in many aspects from the well-studied vertical IGBT. In this paper, the voltage derivative during inductive turnoff for a silicon-on-insulator (SOI) lateral IGBT (LIGBT) is analyzed in detail. A complete model which accounts for the voltage rise is implemented through an accurate calculation of the equivalent output capacitance. The model is in excellent agreement with two-dimensional simulations and experimental results across a wide range of conditions. Further, the paper shows that previously proposed models, which targeted the vertical IGBT, are not adequate for the description of the turnoff voltage rise in the LIGBT.

The Analysis of Electrothermal Conductivity Characteristics for SOI(SOS) LIGBT with latch-up

The electrothermal characteristics of a high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) using thin silicon on insulator (SOI) and silicon on sapphire (SOS) such as thermal conductivity and sink is analyzed by MEDICI. The device simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for modeling of the thermal behavior of SOI devices. In this paper we simulated the thermal conductivity and temperature distribution of a SOI LIGBT with an insulator layer of SiO and O at before and after latch-up and verified that the SOI LIGBT with the O insulator had good thermal conductivity and reliability.

A New Silicon-on-Insulator Lateral Insulated-Gate Bipolar Transistor with Dual-Channel Structure

To improve the latch-up and forward voltage drop properties of the silicon-on-insulator (SOI) lateral insulated-gate bipolar transistor (LIGBT), a new SOI LIGBT structure is proposed and fabricated. The new device employs a dual-channel structure in order to enable more electrons to flow into the n-drift layer and to improve the latch-up characteristic.

A dual-gate shorted-anode silicon-on-insulator lateral insulated gate bipolar transistor with floating ohmic contact for suppressing snapback and fast switching characteristics

A new dual-gate shorted-anode SOI (silicon-on-insulator) LIGBT (lateral insulated gate bipolar transistor), which suppresses the snapback effectively with gates signal of the same polarity, is proposed and verified by numerical simulation. The suppression of the snapback in I–V characteristics is obtained by initiating the hole injection by employing the dual gate and FOC (floating ohmic contact) in the new device. The proposed device eliminates the snapback completely and has a low forward voltage drop compared with conventional SA-LIGBT (shorted anode lateral insulated gate bipolar transistor). Snapback of SA-LIGBT occurs at anode voltage 11 V, but in case of the proposed device, the snapback phenomenon is completely eliminated. Also, by employing the FOC, the drive signals of two gates are of an identical polarity. Therefore the proposed device requires no additional power supply, which is a necessity for driving conventional dual-gate SA-LIGBT.

A Trench-Gate Silicon-on-Insulator Lateral Insulated Gate Bipolar Transistor with the p+ Cathode Well

A trench-gate silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) with the p+ cathode well is proposed to improve the latch-up characteristics, and the improved characteristics are verified numerically by MEDICI simulation. It is found that the trench-gate SOI LIGBT exhibits at least 6 times larger latch-up capability than the conventional devices. The enhanced latch-up capability of the trench-gate SOI LIGBT is obtained due to the fact that the hole current in the device bypasses the resistance of the p body region which is the source of the latch-up and reaches the cathode via the p+ cathode well.

A reliability growth model : Steven S. Tung. Proc. a. Reliab. Maintainab. Symp. 490 (1984)

The high-voltage interconnection (HVI) issue becomes severe in the high-voltage monolithic ICs when single-layer metal is used for lowering the cost. This paper proposes a dual deep-oxide trenches (DDOT) structure for 500 V Silicon-on-Insulator Lateral Insulated Gate Bipolar Transistor (SOI-LIGBT) to shield the influence of HVI on the breakdown voltage. Compared with the conventional DDOT structure, HVI region of the proposed DDOT structure is shrunk by employing a shallow trench (T1) and a deep trench (T2). Besides the breakdown mechanism in the off-state, the current density and impact ionization rate distributions in the on-state of the proposed structure are also investigated. The experiments demonstrate that the proposed DDOT structure can fully shield the influence of HVI with significant reduction in the area of silicon region beneath the HVI. With almost the same off-state breakdown voltage (BVoff) of 550 V as the conventional DDOT structure, the length of the silicon region under the HVI in the proposed structure is shortened from 45 μm to 15 μm. Meanwhile, no on-state breakdown voltage (BVon) degradation is observed according to the measured results. The new method proposed in this work can also be used for other types of high-voltage devices such as LDMOS and free-wheeling diode in SOI Monolithic ICs.