Silicon Metal Oxide Semiconductor Field-effect Transistors Research Articles

Effect of high temperature annealing on cryogenic transport properties of silicon MOSFETs with a thin SiO2/HfO2 stacked dielectric

Quantum computing is expected to break the computing power bottleneck with the help of quantum superposition and quantum entanglement. In order to fabricate fault-tolerant quantum computers for encoding quantum information, it is important to improve the cryogenic mobility of silicon-based metal oxide semiconductor field effect transistors (MOSFETs) with a thin gate dielectric layer as much as possible. Based on a thin SiO2/HfO2 stacked dielectric, we investigate the effect of post-deposition annealing (PDA) temperature on the MOSFET cryogenic transport properties. The results show that silicon atoms will diffuse into the HfO2 to form silicates during PDA, leading to the HfO2 dielectric constant decrease. As the PDA temperature increases, the proportion of monoclinic hafnium oxide decreases and the tetragonal phase increases gradually. The oxygen vacancy content increases gradually, resulting in fixed charge density increases and the mobility decreases. The contribution of the forming gas annealing (FGA) to the mobility enhancement is clarified and the HfO2 recrystallization process is revealed from the perspective of long-time annealing. Finally, the mobility peak of silicon MOSFETs with thin SiO2/HfO2 dielectrics is enhanced to 1387 cm2(V·s)−1 at 1.6 K, which provides a technical pathway for the development of silicon-based quantum computation.

Design and Comparative Analysis of an Ultra-Highly Efficient, Compact Half-Bridge LLC Resonant GaN Converter for Low-Power Applications

For low-power applications, this paper presents the development and design of a compact and ultra-highly efficient half-bridge LLC resonant converter. By using Galium Nitride (GaN) devices and high-efficient magnetics, the efficiency and power density of resonant converters can be improved. Compared to Silicon MOSFETs, GaN high-electron-mobility transistors (GaN HEMT) have a lower output capacitance and gate charge, resulting in lower driving loss and shorter dead times. Consequently, the proposed LLC converter based on GaN devices has excellent performance characteristics such as ultra-high efficiency, low switching losses, compact size, high voltage endurance, high operating temperature and high operating frequency. Furthermore, the proposed resonant converter features soft switching properties that ensure that the switches and diodes on the primary side are always switched at zero voltage and current. By doing so, LLC resonant converter switching losses are significantly reduced by up to 3.1%, and an overall efficiency of 98.5% is achieved. The LLC resonant converter design with GaN HEMT has great advantages over Si MOSFET solution regarding efficiency, overall losses, switching loose and power factor correction. A 240 W, 240 V to 60 V half-bridge GaN HEMT LLC resonant converter is simulated with a switching frequency of 75 KHz, along with the comparative analysis of the Si metal oxide semiconductor field effect transistor (MOSFET) solution. Moreover, the design and analysis of highly efficient magnetics with a power factor of 0.99 at full load is presented. A 240-Watt single stage LED driver with power factor correction is also designed to verify and compare the performance of proposed LLC resonant converter.

Design and Implementation of a Paralleled Discrete SiC MOSFET Half-Bridge Circuit with an Improved Symmetric Layout and Unique Laminated Busbar

Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) have many advantages compared to silicon (Si) MOSFETs: low drain-source resistance, high thermal conductivity, low leakage current, and high switching frequency. As a result, Si MOSFETs are replaced with SiC MOSFETs in many industrial applications. However, there are still not as many SiC modules to customize for each application. To meet the high-power requirement for custom applications, paralleling discrete SiC MOSFETs is an essential solution. However, it comes with many technical challenges; inequality in current sharing, different switching losses, different transient characteristics, and so forth. In this paper, the detailed MATLAB®/Simulink® Simpscape model of the SiC MOSFET from the datasheet and the simulation of the half-bridge circuit are investigated. Furthermore, this paper proposes the implementation of the four-paralleled SiC MOSFET half-bridge circuit with an improved symmetric gate driver layout. Moreover, a unique laminated busbar connected directly to the printed circuit board (PCB) is proposed to increase current and thermal capacity and decrease parasitic effects. Finally, the experimental and simulation results are presented using a 650 V SiC MOSFET (CREE) double-pulse test (DPT) circuit. The voltage overshoot problems and applied solutions are also presented.

Study of Carrier Mobilities in 4H-SiC MOSFETS Using Hall Analysis.

The channel conduction in 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs) are highly impacted by charge trapping and scattering at the interface. Even though nitridation reduces the interface trap density, scattering still plays a crucial role in increasing the channel resistance in these transistors. In this work, the dominant scattering mechanisms are distinguished for inversion layer electrons and holes using temperature and body-bias-dependent Hall measurements on nitrided lateral 4H-SiC MOSFETs. The effect of the transverse electric field () on carrier mobility is analyzed under strong inversion condition where surface roughness scattering becomes prevalent. Power law dependencies of the electron and hole Hall mobility for surface roughness scattering are determined to be and , respectively, analogous to those of silicon MOSFETs. Moreover, for n-channel MOSFETs, the effect of phonon scattering is observed at zero body bias, whereas in p-channel MOSFETs, it is observed only under negative body biases. Along with the identification of regimes governed by different scattering mechanisms, these results highlight the importance of the selection of substrate doping and of in controlling the value of channel mobility in 4H-SiC MOSFETs.

Low-Stress and Optimum Design of Boost Converter for Renewable Energy Systems

This paper examines the design and analysis of DC–DC converters for high-power and low-voltage applications such as renewable energy sources (RESs) and comparisons between converters based on switch stresses and efficiency. The RESs including photovoltaic arrays and fuel cell stacks must have enhanced output voltages, such as 380 V DC in the case of a full bridge inverter or 760 V DC in the case of a half bridge inverter, in order to interface with the 220 V AC grid-connected power system. One of the primary difficulties in developing renewable energy systems is enhancing DC–DC converters’ efficiency to enable high step-up voltage conversion with high efficiency and low voltage stress. In the present work, the efficiency, current, and voltage stress of switches of an isolated Flyback boost converter, simple DC–DC Boost converter, and an Interleaved boost converter, are explored and studied relatively. The most suitable and optimized options with a high efficiency and low switching stress are investigated. The more suitable topology is designed and analyzed for the switch technology based on the Silicon-Metal Oxide Semiconductor Field Effect Transistor (Si-MOSFET) and the Gallium Nitride-High Electron Mobility Transistor (GaN-HEMT). The Analytical approach is analyzed in this paper based on efficiency and switching stress. It is explored that GaN HEMT based Flyback boost converter is the best. Finally, the future direction for further improving the efficiency of the proposed boost converter is investigated.

An Overview on MOSFET Drivers and Converter Applications

—The metal oxide semiconductor field effect transistor (MOSFET) drivers are among the main components for most power electronic applications. Increasing the switching frequency from kHz to MHz levels, MOSFETs' current, power and efficiency expectations are increasing. So it needs to find new solutions to design fast drivers. Some of the outcomes and new applications are now silicon carbide MOSFET applications. The focus of this paper is the power MOSFET gate drive requirements in various switch-mode power conversion applications. So a detailed literature review about MOSFET drivers investigates in this study firstly. There are several different MOSFET structures, but the authors focused on the planar-gate counterparts. Primary system and the switching principle of MOSFET's given in this study. The MOSFET gate driver design principles are presented in more detail in this study. Different proposals and applications for power converters are provided with examples. The drivers evaluated and concluded in all ways.

THz linear array scanner in application to the real-time imaging and convolutional neural network recognition

Room temperature linear arrays (up to 160 detectors in array) from silicon metal- oxide-semiconductor field-effect transistors (Si-MOSFETs) have been designed for sub- THz (radiation frequency 140 GHz) close to real-time direct detection operation scanner to be used for detection and recognition of hidden objects. For this scanner, the optical system with aspherical lenses has been designed and manufactured. To estimate the quality of optical system and its resolution, the system modulation transfer function was applied. The scanner can perform real-time imaging with the spatial resolution better than 5 mm at the radiation frequency 140 GHz and contrast 0.5 for the moving object speed up to 200 mm/s and the depth of field 20 mm. The average dynamic range of real time imaging system with 160-detector linear array is close to 35 dB, when the sources with the output radiation power of 23 mW (IMPATT diodes) are used (scan speed 200 mm/s). For the system with 32-detector array, the dynamic range was about 48 dB and for the single-detector system with raster scanning 80 dB with lock-in amplifier. However, in the latter case for obtaining the image with the sizes 20×40 mm and step of 1 mm, the average scanning time close to 15 min is needed. Convolutional neural network was exploited for automatic detection and recognition of hidden items.

Review on Driving Circuits for Wide-Bandgap Semiconductor Switching Devices for Mid- to High-Power Applications.

Wide-bandgap (WBG) material-based switching devices such as gallium nitride (GaN) high electron mobility transistors (HEMTs) and silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are considered very promising candidates for replacing conventional silicon (Si) MOSFETs for various advanced power conversion applications, mainly because of their capabilities of higher switching frequencies with less switching and conduction losses. However, to make the most of their advantages, it is crucial to understand the intrinsic differences between WBG- and Si-based switching devices and investigate effective means to safely, efficiently, and reliably utilize the WBG devices. This paper aims to provide engineers in the power engineering field a comprehensive understanding of WBG switching devices’ driving requirements, especially for mid- to high-power applications. First, the characteristics and operating principles of WBG switching devices and their commercial products within specific voltage ranges are explored. Next, considerations regarding the design of driving circuits for WBG switching devices are addressed, and commercial drivers designed for WBG switching devices are explored. Lastly, a review on typical papers concerning driving technologies for WBG switching devices in mid- to high-power applications is presented.

Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-of-the-Roadmap III–V MOSFETs

Thanks to their superior transport properties, indium gallium arsenide (InGaAs) metal–oxide–semiconductor field-effect transistors (MOSFETs) constitute an alternative to conventional silicon MOSFETs for digital applications at ultrascaled nodes. The successful integration of this technology is challenged mainly by the high defect density in the gate oxide and at the interface with the semiconductor channel, which degrades the electrostatics and could limit the potential benefits over Si. In this work, we: 1) establish a systematic modeling approach to evaluate the performance degradation due to interface traps in terms of electrostatics and transport of InGaAs dual-gate ultrathin body (DG-UTB) FETs and 2) investigate the effects of random interface-trap concentration as another roadblock to the scaling of the technology, due to statistical variability of the threshold voltage. Variability is assessed with a Technology CAD (TCAD) simulator calibrated against multi-subband Monte Carlo (MSMC) simulations. The modeling approach overcomes the TCAD limitations when dealing with ultrathin channels (i.e., below 5 nm) without altering crucial geometrical parameters that would compromise the dependability of the variability analysis. Our results indicate that interface-trap fluctuation becomes comparable with the other variability sources dominating the total variability when shrinking the device dimensions, thus contrasting the trend of reduced variability with scaling. This, in turn, implies that interface and border traps may strongly limit the benefits of InGaAs over Silicon if not effectively reduced by gate process optimization.

Full-Bridge Active-Clamp Forward-Flyback Converter with an Integrated Transformer for High-Performance and Low Cost Low-Voltage DC Converter of Vehicle Applications

This paper presents a full-bridge active-clamp forward-flyback (FBACFF) converter with an integrated transformer sharing a single primary winding. Compared to the conventional active-clamp-forward (ACF) converter, the proposed converter has low voltage stress on the primary switches due to its full-bridge active-clamp structure, which can leverage high performance Silicon- metal–oxide–semiconductor field-effect transistor (Si-MOSFET) of low voltage rating and low channel resistance. Integrating forward and flyback operations allows the proposed converter to have much lower primary root mean square (RMS) current than the conventional phase-shifted-full-bridge (PSFB) converter, while covering wide input/output voltage range with duty ratio over 0.5. The proposed integrated transformer reduces the transformer conduction loss and simplify the secondary structure of the proposed converter. As a result, the proposed converter has several advantages: (1) high heavy load efficiency, (2) wide input voltage range operation, (3) high power density with the integrated transformer, and (4) low cost. The proposed converter is a very promising candidate for applications with wide input voltage range and high power, such as the low-voltage DC (LDC) converter for eco-friendly vehicles.

Gate Damages Induced in SiC Power MOSFETs During Heavy-Ion Irradiation—Part II

This article presents the results of a 2-D finite element simulation study of the gate damages induced by heavy-ion irradiation in SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). The time evolution of the electric field in the gate oxide is studied. Two effects are investigated: the first is associated with the charge deposition in the SiC portion of the MOSFET, with the time evolution studied using the 2-D finite element simulator; the second one results from holes generated during the ion transit, trapped in the gate oxide after the fast electrons have been quickly swept away by the electric field. Two different techniques have been combined for estimating the hole concentration in the gate oxide: the well-known recombination rate was modified to consider the trapped charge yield, as was recently done to better interpret single event gate rupture (SEGR) failure of silicon power MOSFETs. Under ion irradiation test conditions at which the gate damage experimentally starts to be observed, we demonstrate that, because of the ion impact, regardless of the ion linear energy transfer (LET), the peak value of the electric field in the gate oxide becomes practically equal to the oxide breakdown field (~12–15 MV/cm). Moreover, we show that simulations can be used to predict the test conditions at which gate damage starts to appear as a function of LET and the range of heavy ions used in the irradiation experiments.

A Digital-Controlled SiC-Based Solid State Circuit Breaker with Soft Switch-Off Method for DC Power System

Due to the lower on-state resistance, direct current (DC) solid state circuit breakers (SSCBs) based on silicon-carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) can reduce on-state losses and the investment of the cooling system when compared to breakers based on silicon (Si) MOSFETs. However, SiC MOSFETs, with smaller die area and higher current density, lead to weaker short-circuit ability, shorter short-circuit withstand time and higher protection requirements. To improve the reliability and short-circuit capability of SiC-based DC solid state circuit breakers, the short-circuit fault mechanisms of Si MOSFETs and SiC MOSFETs are revealed. Combined with the desaturation detection (DESAT), a “soft turn-off” short-circuit protection method based on source parasitic inductor is proposed. When the DESAT protection is activated, the “soft turn-off” method can protect the MOSFET against short-circuit and overcurrent. The proposed SSCB, combined with the flexibility of the DSP, has the μs-scale ultrafast response time to overcurrent detection. Finally, the effectiveness of the proposed method is validated by the experimental platform. The method can reduce the voltage stress of the power device, and it can also suppress the short-circuit current.

Evidence for mixed phases and percolation at the metal-insulator transition in two dimensions

The in-plane magnetoconductance of the strongly interacting two-dimensional electron system in a silicon MOSFET (metal-oxide-semiconductor-field-effect transistor) exhibits an unmistakeable kink at a well-defined electron density, $n_k$. The kink at $n_k$ is near, but not at the critical density $n_c$ determined from resistivity measurements, and the density at which $n_k$ occurs varies with temperature. These features are inconsistent with expectations for a quantum phase transition. We suggest instead that this is a percolation transition and present a detailed model based on the formation of a mixed insulating and metallic phase within which a metal-insulator transition takes place by percolation.

A New Analytical Tool for the Study of Radiation Effects in 3-D Integrated Circuits: Near-Zero Field Magnetoresistance Spectroscopy

We demonstrate that a new technique, near-zero field magnetoresistance (NZFMR) spectroscopy, can explore radiation damage in a wide variety of devices in a proof-of-concept study. The technique has great potential for the study of atomic-scale mechanisms of radiation damage in 3-D integrated circuits. In our study, we explore radiation damage in structures relevant to 3-D integrated circuits, but not on 3-D test structures themselves. Five structures of great technological importance to 3-D integrated circuits are investigated. We utilize both NZFMR and electrically detected magnetic resonance to investigate radiation effects in these structures. The structures involved in this paper are planar silicon metal–oxide–semiconductor field-effect transistors, silicon–germanium alloy-based transistors, fin-based transistors, silicon dioxide-based flowable oxides, and low-k dielectrics. Our study indicates that NZFMR has great potential in radiation damage studies, with exceptional promise in systems in which more conventional resonance is not possible.

Threshold voltage peculiarities and bias temperature instabilities of SiC MOSFETs

Silicon carbide (SiC) based metal-oxide semiconductor-field-effect-transistors (MOSFETs) are increasingly entering the high power device market. Besides all the well-known benefits which come along with these new generations of switches, the nature of the wide bandgap material and the different properties of the semiconductor-dielectric interface involve some natural peculiarities in threshold voltage variation and bias-temperature-instability (BTI) which differ from comparable silicon (Si) MOSFET counterparts and which need to be understood and assessed. The target of this paper is to highlight such differences, explain their relation to the semiconductor material, challenge their relevance for the application and define their consequences with regard to datasheet specifications. Most of the new effects can be understood by means of simple physical models and do not compromise the reliability of the device. However, it turns out that the standard test procedures typically used to characterize threshold voltage and threshold voltage drifts for Si devices need to be adapted for SiC MOSFETs. A new measure-stress-measure procedure for BTI evaluation of SiC MOSFETs is proposed which allows distinguishing between reversible threshold voltage hysteresis and more permanent threshold voltage drift (BTI). The measurement pattern is then used to assess the VTH stability of recently launched SiC MOSFET parts. The tested devices differ considerably in BTI drift amplitude and drift variation. The differences are attributed to variations in device processing and device design.

Silicon Millimeter-Wave, Terahertz, and High-Speed Fiber-Optic Device and Benchmark Circuit Scaling Through the 2030 ITRS Horizon

This paper reviews the technology requirements of future 100–300-GHz millimeter-wave (mm-wave) systems-on-chip (SOI) for high data rate wireless and sensor applications, as well as for 100–300-GBaud fiber-optic communication systems. Measurements of state-of-the-art silicon metal–oxide–semiconductor field-effect transistors (MOSFETs), SiGe heterojunction bipolar transistors (HBTs), and of a variety of HBT-HBT and MOS-HBT cascodes are presented from dc to 325 GHz. The challenges facing mm-wave MOSFET and SiGe HBT device and benchmark circuit scaling toward 2–3-nm gate length and beyond 2-THz transistor $f{\mathrm {MAX}}$ are discussed for the first time based on technology computer-aided design (TCAD) and atomistic simulations. Finally, simulations of the scaling of the SiGe HBT analog and mixed-signal mm-wave benchmark circuit performance across future technology nodes predict that PAs with 45% power added efficiency (PAE) at 220 GHz, track and hold amplifiers (THAs) with over 140-GHz bandwidth, and transimpedance amplifiers (TIAs) with 250-GHz bandwidth and less than 5-dB noise figure will become feasible by 2030. Comparison of simulations and measurements for representative benchmark circuits such as TIAs, THAs, linear modulator drivers, digital-to-analog converters (DACs), and power amplifiers (PAs), fabricated in advanced SiGe BiCMOS and nanoscale SOI complementary metal–oxide–semiconductor (CMOS) technologies, and operating at 120 Gb/s and above 100 GHz, respectively, are presented to support the credibility of the benchmark circuit scaling exercise.

A Model for Neutral Defect Limited Electron Mobility in Strained-Silicon Inversion Layers

On the strained silicon metal–oxide–semiconductor field-effect transistors (MOSFETs), we show how to derive a formalism dealing with the scattering of a 2-D electron by a neutral defect. The corresponding neutral defect limited inversion-layer electron mobility, $\mu _{n}$ , is calculated in the momentum relaxation time approximation. The calculated results lead to a new analytical model: $\mu _{n} =cN_{n} ^{-1}$ , where $N_{n}$ is the neutral defect density per unit area and ${c}$ is the coefficient independent of the inversion-layer density, the strain, and the temperature. The validity and applicability of the model are confirmed by citing three independent experiments on strained silicon MOSFETs undergoing different implantation sources and different annealing budgets. Importantly, this paper clarifies for the first time that strain will not change neutral defect limited mobility unless changing the neutral defect density. This reasonably explains the two experimental observations during implantation and annealing: 1) the implantation-induced strain relaxation in strained sample does not occur and 2) the neutral defect density is much higher in strained sample than in unstrained sample.

Predictive dead time controller for GaN‐based boost converters

A dynamic dead time controller is presented, specifically intended to operate in synchronous boost converters based on GaN field-effect transistor switches. These transistors have a reduced stored charge with respect to silicon metal–oxide–semiconductor field-effect transistors with similar breakdown voltage and series resistance, and can operate at higher frequencies with reduced switching losses. On the other hand, the voltage drop in reverse conduction is typically more than doubled with respect to silicon devices resulting in relevant power losses during the free-wheeling phases. Therefore, dynamic control of dead time can be profitably applied even in converters operating in the tens of volts range. The device presented in this study controls the switching delays taking into account both variations of the fall/rise times and of the turn-off/on delays, in order to keep dead time within a range of a few nanoseconds above its minimum value. A discrete-component prototype was designed, built in a synchronous boost converter and extensively tested at 1–2 MHz switching frequency, in a range of operating parameters corresponding to significant variations of the switching times (currents in the 1–6 A range, output voltage up to 50 V). The prototype demonstrated the capability to match dead time to actual operating conditions with a smooth and fast transient response.

Improvement of charge-pumping electrically detected magnetic resonance and its application to silicon metal–oxide–semiconductor field-effect transistor

Charge-pumping electrically detected magnetic resonance (CP EDMR), or EDMR in the CP mode, is improved and applied to a silicon metal–oxide–semiconductor field-effect transistor (MOSFET). Real-time monitoring of the CP process reveals that high-frequency transient currents are an obstacle to signal amplification for EDMR. Therefore, we introduce cutoff circuitry, leading to a detection limit for the number of spins as low as 103 for Si MOS interface defects. With this improved method, we demonstrate that CP EDMR inherits one of the most important features of the CP method: the gate control of the energy window of the detectable interface defects for spectroscopy.

Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless Cylindrical Surrounding-Gate MOSFETs

Abstract When the traditional planar metal-oxide-semiconductor-field-effect transistors (MOSFETs) encounter insurmountable bottleneck of static power dissipation, junctionless transistor (JLT) becomes a promising candidate for sub-22 nm nanoscale devices due to its simpler fabrication process and better short-channel performances. Subthreshold behaviors dominate the standby power of nanoscale JLTs. In this chapter, a physics-based analytical model of electrostatic potential for both silicon and germanium short-channel junctionless cylindrical surrounding-gate (JLCSG) MOSFETs operated in the subthreshold regime is proposed, in which the full twodimensional (2D) Poisson’s equation is solved in the channel region by a method of series expansion. The expression of the proposed electrostatic potential is completely rigorous and explicit. Based on this result, the expressions of threshold voltage, subthreshold drain current, and subthreshold swing for JLCSG MOSFETs are derived. Subthreshold behaviors are studied in detail by changing different device parameters and bias conditions, including doping concentration, channel radius, gate length, gate equivalent oxide layer thickness, drain voltage, and gate voltage. Results predicted by all the analytical models agree well with numerical solutions from the three-dimensional simulator. These analytical models can be used to investigate the operating mechanisms of nanoscale JLCSG MOSFETs and to optimize their device performances.