Silicon Field Effect Transistors Research Articles

Quantum Mechanical Simulation of Hole Transport in <I>p</I>-Type Si Schottky Barrier MOSFETs

A full quantum-mechanical simulation of p-type nanowire Schottky barrier metal oxide silicon field effect transistors (SB-MOSFETs) is performed by solving the three-dimensional Schrödinger and Poisson's equations self-consistently. The non-equilibrium Green's function (NEGF) approach is adopted to treat hole transport, especially quantum tunneling through SB. In this work, p-type nanowire SB-MOSFETs are simulated based on the 3-band k.p method, using the k.p parameters that were tuned by benchmarking against the tight-binding method with sp3s* orbitals. The device shows a strong dependence on the transport direction, due to the orientation-sensitive tunneling effective mass and the confinement energy. With regard to the subthreshold slope, the [110] and [111] oriented devices with long channel show better performance, but they are more vulnerable to the short channel effects than the [100] oriented device. The threshold voltage also shows a greater variation in the [110] and [111] oriented devices with the decrease of the channel length.

Half-bridge converter based on switched-capacitor resonance without using deadtime control for automotive applications

For virtually all converters and inverters, it is necessary to take care of shot-through and deadtime in the half-bridge subcircuits. Floating gate drive designs are also needed. The additional cost to realise these features becomes a concern in low power applications. This study presents a centre-tapped inductor method added to the bridge to satisfy these constraints cost-effectively. The shoot-through current is under controlled. Using push-pull P and N channel metal-oxide silicon field-effect transistors, the floating or level-shift gate drive can be eliminated and the converter becomes simple. The proposed method has been successfully applied to switched capacitor resonant converter. Formulations of the overlapping and resonant equations have also been developed. It is found that the current in the centre-tapped inductor can be transferred to the resonant inductor with the proposed circuitry with no additional loss involved in the design. Moreover, all the current is under zero-current switching. The design has been validated experimentally and high efficiency is realised using the proposed design.

Electrically Detected Magnetic Resonance of Neutral Donors Interacting with a Two-Dimensional Electron Gas

We have measured the electrically detected magnetic resonance of donor-doped silicon field-effect transistors in resonant X- (9.7 GHz) and W-band (94 GHz) microwave cavities. The two-dimensional electron gas resonance signal increases by 2 orders of magnitude from X to W band, while the donor resonance signals are enhanced by over 1 order of magnitude. Bolometric effects and spin-dependent scattering are inconsistent with the observations. We propose that polarization transfer from the donor to the two-dimensional electron gas is the main mechanism giving rise to the spin resonance signals.

Modeling Interconnects for Post-CMOS Devices and Comparison With Copper Interconnects

Power dissipation in charge-based technology is the biggest roadblock toward miniaturizing circuits. Quantum-mechanical tunneling and subthreshold leakage current will ultimately limit scaling of silicon field-effect transistors. To continue Moore's law scaling, it is imperative that devices working with a state variable other than electron charge are sought for. Examples of alternate state variables include electron spins, pseudo-spins in graphene, direct and indirect excitons, plasmons, and phonons. At the same time, interconnection aspects of devices utilizing novel state variables must be considered early on. This paper provides a framework to quantify energy dissipation in interconnects for novel state variables. Models for energy per bit are then used along with previously derived models for delay of interconnects for novel state variables to compare performance and energy dissipation of novel interconnects with complementary metal-oxide-semiconductor (CMOS) interconnects. Comparison results provide important insights into material, device, and circuit implications of post-CMOS technologies.

A High-Linearity Low-Noise Amplifier with Variable Bandwidth for Neural Recoding Systems

This paper describes a low-noise amplifier with multiple adjustable parameters for neural recording applications. An adjustable pseudo-resistor implemented by cascade metal–oxide–silicon field-effect transistors (MOSFETs) is proposed to achieve low-signal distortion and wide variable bandwidth range. The amplifier has been implemented in 0.18 µm standard complementary metal–oxide–semiconductor (CMOS) process and occupies 0.09 mm2 on chip. The amplifier achieved a selectable voltage gain of 28 and 40 dB, variable bandwidth from 0.04 to 2.6 Hz, total harmonic distortion (THD) of 0.2% with 200 mV output swing, input referred noise of 2.5 µVrms over 0.1–100 Hz and 18.7 µW power consumption at a supply voltage of 1.8 V.

A simple four-point-bending setup for measurement of mechanical stress on silicon field-effect transistors

A simple four-point-bending setup integrated with a foil strain gauge is presented for the direct measurement of mechanical stress (MS) on metal–oxide–semiconductor field-effect transistors (MOSFETs). The magnitude of the external MS applied to MOSFETs can be directly obtained through the resistance change due to strain in the strain gauge mounted on the wafer strip. Then the resistance change in the strain gauge is detected in a Wheatstone quarter-bridge circuit. In addition, the validity of the direct stress measurement is confirmed by using the finite element analysis. Finally, through the direct stress measurement on MOSFETs, the longitudinal piezoresistance coefficients appear to be fairly comparable with the reported values in earlier literatures. The stress measurement is also expected to be applicable to the evaluation of uniaxial-process-induced strained MOSFETs.

Electrically detected magnetic resonance in a W-band microwave cavity

We describe a low-temperature sample probe for the electrical detection of magnetic resonance in a resonant W-band (94 GHz) microwave cavity. The advantages of this approach are demonstrated by experiments on silicon field-effect transistors. A comparison with conventional low-frequency measurements at X-band (9.7 GHz) on the same devices reveals an up to 100-fold enhancement of the signal intensity. In addition, resonance lines that are unresolved at X-band are clearly separated in the W-band measurements. Electrically detected magnetic resonance at high magnetic fields and high microwave frequencies is therefore a very sensitive technique for studying electron spins with an enhanced spectral resolution and sensitivity.

Silicon field effect transistors as dual-use sensor-heater hybrids.

We demonstrate the temperature mediated applications of a previously proposed novel localized dielectric heating method on the surface of dual purpose silicon field effect transistor (FET) sensor-heaters and perform modeling and characterization of the underlying mechanisms. The FETs are first shown to operate as electrical sensors via sensitivity to changes in pH in ionic fluids. The same devices are then demonstrated as highly localized heaters via investigation of experimental heating profiles and comparison to simulation results. These results offer further insight into the heating mechanism and help determine the spatial resolution of the technique. Two important biosensor platform applications spanning different temperature ranges are then demonstrated: a localized heat-mediated DNA exchange reaction and a method for dense selective functionalization of probe molecules via the heat catalyzed complete desorption and reattachment of chemical functionalization to the transistor surfaces. Our results show that the use of silicon transistors can be extended beyond electrical switching and field-effect sensing to performing localized temperature controlled chemical reactions on the transistor itself.

High-k dielectric Al2O3 nanowire and nanoplate field effect sensors for improved pH sensing

Over the last decade, field-effect transistors (FETs) with nanoscale dimensions have emerged as possible label-free biological and chemical sensors capable of highly sensitive detection of various entities and processes. While significant progress has been made towards improving their sensitivity, much is yet to be explored in the study of various critical parameters, such as the choice of a sensing dielectric, the choice of applied front and back gate biases, the design of the device dimensions, and many others. In this work, we present a process to fabricate nanowire and nanoplate FETs with Al(2)O(3) gate dielectrics and we compare these devices with FETs with SiO(2) gate dielectrics. The use of a high-k dielectric such as Al(2)O(3) allows for the physical thickness of the gate dielectric to be thicker without losing sensitivity to charge, which then reduces leakage currents and results in devices that are highly robust in fluid. This optimized process results in devices stable for up to 8h in fluidic environments. Using pH sensing as a benchmark, we show the importance of optimizing the device bias, particularly the back gate bias which modulates the effective channel thickness. We also demonstrate that devices with Al(2)O(3) gate dielectrics exhibit superior sensitivity to pH when compared to devices with SiO(2) gate dielectrics. Finally, we show that when the effective electrical silicon channel thickness is on the order of the Debye length, device response to pH is virtually independent of device width. These silicon FET sensors could become integral components of future silicon based Lab on Chip systems.

Array of silicon field effect transistors to detect charges propagation in neurons circuit

ABSTRACTWe present transport properties of silicon nanowires field effect transistors realized on SOI substrates and their application to probe electrical activity of biological objects. Devices are sensitive to short and weak voltage pulses (ms, mV) applied in an electrolyte solution, allowing a future efficient detection of neuronal activity. For that purpose, the organized growth of neuronal cells along chosen patterns has been obtained, leading to an accurate coupling with silicon nanowire field effect transistors. Both network architectures, neural and semiconducting, have been designed to study some aspects of the propagation and the processing of information by the nervous system.

In Quest of the “Next Switch”: Prospects for Greatly Reduced Power Dissipation in a Successor to the Silicon Field-Effect Transistor

Reduced power dissipation relative to the field-effect transistor (FET) is a key attribute that should be possessed by any device that has a chance of supplanting the FET as the ubiquitous building block for complex digital logic. We outline the possible physical approaches to achieving this attribute, and illustrate these approaches by citing current exploratory device research. We assess the value of the key exploratory research objectives of the semiconductor industry-sponsored Nanoelectronics Research Initiative (NRI) in the light of this pressing need to reduce dissipation in future digital logic devices.

High-density Nano-scale N-channel Trench-gated MOSFETs Using the Self-aligned Technique

We propose a novel process technology for fabricating a very high density n-channel trench-gate metal oxide silicon field effect transistor (MOSFET) by using an oxide spacer and self-aligned techniques. Due to this nano-scale technology, the cell pitch of the trench-gate MOSFET could be reduced to 3.0 {mu}m, which resulted in an increase in the cell density and in current driving capability. By reducing masks to four layers, a cost-effective process was available. The self-aligned technique also permits a narrow width of the trench gate on the scale of 300 nm. The fabricated device exhibits a specific on-resistance of 1.4 m{Omega}{center_dot}cm{sup 2} for a breakdown voltage of 114.8 V. Moreover, the long-term gate oxide's integrity was improved by adopting corner rounding and hydrogen annealing technologies.

A comparative study of self-heating effect of nMOSFETs fabricated on SGOI and SGSOAN substrates

In this work, for the first time, the electrical and thermal characteristics of strained Si/SiGe nanoscale n type metal–oxide–silicon field-effect transistors (MOSFETs) with silicon-on-aluminum nitride (SOAN) substrate are investigated by ISE TCAD. This novel structure is named as SGSOAN nMOSFET. A comparative study of self-heating effect (SHE) of nMOSFETs fabricated on SGOI and SGSOAN are presented in this paper. Numerical study results show that this novel SGSOAN structure can greatly eliminate excessive self-heating in devices, which gives a more promising application for SGOI to work at high temperature.

Ferroelectric field effect transistors using very thin ferroelectric polyvinylidene fluoride copolymer films as gate dielectrics

We report electrical characterization of memory elements consisting of a p-type silicon field-effect transistor incorporating a ferroelectric polymer Langmuir–Blodgett film into the gate insulator to produce bistability through polarization hysteresis. The thin gate insulator, consisting of a 10 nm thick silicon oxide layer and a 35 nm thick ferroelectric polymer film, enabled bistable operation at 4 V. Device hysteresis as a function of gate voltage was evident both in the device capacitance, which was measured between the gate and drain, and in the source-drain conductance. The ferroelectric film polarization was not saturated, even up to operating voltages of 10 V. This is likely the reason for the short state retention of less than 10 s at room temperature. The hysteresis vanished as the sample was heated toward the ferroelectric-paraelectric phase transition temperature, showing that the bistability was due to ferroelectric polarization reversal.

Low Contact Resistivity with Low Silicide/p+-Silicon Schottky Barrier for High-Performance p-Channel Metal–Oxide–Silicon Field Effect Transistors

A current drivability improvement of p-channel metal–oxide–silicon field effect transistors (MOSFETs) is necessary for the performance enhancement of complementary metal–oxide–semiconductor (CMOS) circuits. In this paper, we present the key technology for fabricating indispensable CMOS circuits with a small Schottky barrier height and a low contact resistance for p-type silicon using Pd2Si. We fabricated a Pd2Si gate Schottky barrier diode and a Kelvin pattern on silicon. The measured Schottky barrier height is 0.29 eV for p-type silicon. We also realized a very low contact resistivity of 3.7 ×10-9 Ω cm2 for the p+ region of silicon. The p-channel MOSFET with Pd2Si source/drain contacts realized a good characteristic, that is, a small off current. The technology developed in this work involves silicide formation for source/drain contacts of p-channel MOSFETs, which is expected to realize the performance enhancement of MOSFETs.

Dual-Gate Single-Electron Transistor with Silicon Nano Wire Channel and Surrounding Side Gates

In this paper, we propose a novel self-aligned dual-gate single-electron transistor having nano wire channel and surrounding side gates. By restricting the control gate effect to the top surface of the channel and intensifying the depletion effect through the surrounding side gates, the parasitic metal–oxide–silicon field-effect transistor (MOSFET) current and the quantum dot size are expected to be decreased. These advantages of the proposed structure are investigated through three-dimensional (3D) device simulation. In addition, the devices are fabricated by utilizing the silicon process and their electrical characteristics are analyzed at both room temperature and low temperature. Also, diverse device parameters are extracted from the measurement results, and they are systematically compared.

Nanowire platform for mapping neural circuits

Biological systems consist of a myriad of highly interactive and complex interconnections and pathways across multiple orders of length and time scales. Natural neuronal networks are valuable examples of such systems because they are important for understanding how the brain functions. Monitoring activities of a large number of neurons and intercommunication among them is critical for studying neuronal networks, for which passive microfabricated multielectrode arrays (MEAs) (1) and active planar silicon field effect transistor (FET) arrays (2) have been the two popular techniques. Now, a unique and more powerful technique has been developed, as demonstrated by Qing et al. in PNAS (3). The authors show that neuronal networks can now be studied with much higher spatial and temporal resolution while obtaining higher sensitivity of extracellular recording.

Terahertz heterodyne detection with silicon field-effect transistors

We report on the detection of electromagnetic radiation at 0.65 THz by silicon field-effect transistors operated in heterodyne mode. Aiming at terahertz imaging with numerous pixels in a focal-plane array, we explore the improvement of the dynamic range achieved over power detection when the local-oscillator (LO) power is distributed quasioptically onto all detectors. These consist of resonantly antenna-coupled complementary metal-oxide-semiconductor transistors with a gate length of 0.25 μm, and each has an integrated voltage amplifier. With a LO power of 2 μW per detector, the noise-equivalent power amounts to 8 fW/Hz, leading to an estimated improvement of the dynamic range by 29 dB.

Organic Gate Silicon Field Effect Transistors with Poly Methylmethacrylate Films for Science Education

We have developed an easy fabrication method of Si field effect transistors (FETs) with poly (methyl methacrylate) (PMMA) gate films for science education. In this process, we can easily fabricate the silicon FETs only by means of metal deposition and thermal diffusion without any lithography processes. The organic isolation films of PMMA can be deposited by casting or painting at room temperature in air. The metal-organic-semiconductor FETs with PMMA exhibited almost the same drain current — gate voltage characteristics as those of conventional Si metal-oxide-semiconductor FETs, which are suitable for the education material of semiconductor engineering. The organic gate Si FETs can be used not only for education but also as thin film transistors for active matrix displays.

Room temperature piezoelectric displacement detection via a silicon field effect transistor

An electromechanical oscillator embedded with a two dimensional electron gas is capacitively coupled to a silicon field effect transistor (Si-FET). The piezovoltage induced by the mechanical motion modulates the current passing through the Si-FET enabling the electromechanical oscillator’s position to be monitored. When the Si-FET is biased at its optimal point, the motion induced piezovoltage can be amplified resulting in a displacement sensitivity of 6×10−12 mHz−1/2 for a 131 kHz GaAs resonator which is among the highest recorded for an all-electrical room temperature detection scheme.