Low Contact Resistivity with Low Silicide/p+-Silicon Schottky Barrier for High-Performance p-Channel Metal–Oxide–Silicon Field Effect Transistors

Abstract

A current drivability improvement of p-channel metal–oxide–silicon field effect transistors (MOSFETs) is necessary for the performance enhancement of complementary metal–oxide–semiconductor (CMOS) circuits. In this paper, we present the key technology for fabricating indispensable CMOS circuits with a small Schottky barrier height and a low contact resistance for p-type silicon using Pd2Si. We fabricated a Pd2Si gate Schottky barrier diode and a Kelvin pattern on silicon. The measured Schottky barrier height is 0.29 eV for p-type silicon. We also realized a very low contact resistivity of 3.7 ×10-9 Ω cm2 for the p+ region of silicon. The p-channel MOSFET with Pd2Si source/drain contacts realized a good characteristic, that is, a small off current. The technology developed in this work involves silicide formation for source/drain contacts of p-channel MOSFETs, which is expected to realize the performance enhancement of MOSFETs.