Epitaxial Silicon Layers Research Articles

Numerical and experimental investigation of the effect of side injectors on the deposition rate near the wafer edge during atmospheric pressure chemical vapor deposition

In this study, the effect of side injection on the deposition rate near the wafer edge is investigated through a numerical simulation and in experimental studies. The main purpose is to maintain the uniformity of the silicon epitaxial layer in region of the wafer edge. The results indicate that the deposition rate near the wafer edge can be changed when the momentum of the jet is sufficient to push the streamlines originating from the side injector to touch the wafer edge. The jet momentum can be increased by increasing the inlet velocity and the Trichlorosilane (TCS) mass fraction of the side injector. The deposition rate in the wafer edge region increases when the TCS mass fraction is higher. It is clear that the momentum of the side injector jet determines the region affected, while the TCS mass fraction changes the deposition rate in the affected region. Both experimental and numerical results show that with a suitable jet velocity and TCS mass fraction, the deposition rate in the edge region can be tuned while maintaining almost the same deposition rate in the central region of the wafer. The non-uniformity caused by a sudden drop in the deposition rate in the edge region of the wafer without the use of side injector can be significantly improved by installing a side injector and applying the proper operating conditions. The numerical results are in good agreement with the experimental ones.

Energy calibration through X-ray absorption of the DECAL sensor, a monolithic active pixel sensor prototype for digital electromagnetic calorimetry and tracking

In calorimetry, the predominant detection principle is to measure the energy deposited by particles within a shower initiated by an incident particle. An alternative concept is a sampling calorimeter where the highly granular active layers rather measure the number of secondary particles in the shower by detecting hits through binary readout similar to sensors for tracking applications. In this context, the DECAL sensor is a fully-depleted monolithic active pixel sensor prototype with reconfigurable readout for digital electromagnetic calorimetry and tracking. Its 64 × 64 pixels with a pitch of 55 µm are fabricated in a modified TowerJazz 180 nm CMOS imaging process using a 25 µm epitaxial silicon layer. The readout at 40 MHz is configurable in counting hits in the sensor grouped as either 64 strips or 4 pads. In this article, we present the energy calibration of this sensor using a gamma source of americium-241 as well as X-ray fluorescence at various wavelengths. The uniformity of the pixel responses is shown, allowing the summation of counts across all pixels. By that, two standalone energy calibration methods are developed that describe the X-ray absorption in the energy range of 4–60 keV and agree with each other. The signal pulse height is related to the absorbed photon energy with a 5.54 ± 0.37 mV/keV scale which corresponds to a conversion gain of cg = 19.95 ± 1.32 μV/e−. The relative energy resolution for photon absorption is found to be σE/E = 11.8 ± 3.0%. The absolute counts observed with the DECAL sensor agree with expectations and substantiate the assumption of a fully depleted epitaxial layer. The understanding of the photon absorption is an important input for further development of the sensor towards a multi-layer calorimeter.

New equations to calculate carrier recombination lifetime of silicon epitaxial layer, based on open circuit voltage decay method

Abstract New equations for recombination lifetime calculation based on the open circuit voltage decay (OCVD) method were proposed. The new equations can yield accurate recombination lifetime values of the i-layer of PiN diodes in which a silicon epitaxial layer is employed, by eliminating the effects of carrier diffusion into p+ and n+ layers from the i-layer of PiN diodes, carrier injection into the i-layers from the depletion layer of PiN diodes, and surface recombination on the side wall of PiN diodes. To verify the effectiveness of the new equations, OCVD measurements were performed by employing technology computer-aided design (TCAD) simulation and actual PiN diodes. Although the calculated values implied the effect of epitaxial layer thickness, they were consistent with the results obtained under assumed lifetime conditions for TCAD simulation, the theory of recombination lifetime, and results in other reports.

Numerical simulation analysis of carbon defects in the buffer on vertical leakage and breakdown of GaN on silicon epitaxial layers

Carbon doping in GaN-on-Silicon (Si) epitaxial layers is an essential way to reduce leakage current and improve breakdown voltage. However, complicated occupy forms caused by carbon lead to hard analysis leakage/breakdown mechanisms of GaN-on-Si epitaxial layers. In this paper, we demonstrate the space charge distribution and intensity in GaN-on-Si epitaxial layers from 0 to 448 V by simulation. Depending on further monitoring of the trapped charge density of CN and CGa in carbon-doped GaN at 0.1 μm, 0.2 μm, 1.8 μm and 1.9 μm from unintentionally doped GaN/carbon-doped GaN interface, we discuss the relationship between space charge and plateau, breakdown at CN concentrations from 6 × 1016 cm−3 to 6 × 1018 cm−3. The results show that CN in different positions of carbon-doped GaN exhibits significantly different capture and release behaviors. By utilizing the capture and release behavior differences of CN at different positions in carbon-doped GaN, the blocking effect of space charge at unintentionally doped GaN/carbon-doped GaN interface on electron conduction was demonstrated. The study would help to understand the behavior of CN and CGa in GaN-on-Si epitaxial layers and more accurate control of CN and CGa concentration at different positions in carbon-doped GaN to improve GaN-on-Si device performance.

Growth of 4H-SiC epitaxial layers at temperatures below 1500 °C using trichlorosilane (TCS)

TCS (SiHCl3) is widely used in the rapid growth of SiC. However, in the study of using TCS to grow 4H-SiC, the growth temperature is mainly concentrated in 1550–1650 °C, and the research on lower growth temperature is lacking. In this study, TCS was used as the silicon precursor and epitaxial layers were grown in the temperature range of 1350–1500 °C. The results show that the single crystal type 4H-SiC epitaxial layer with good quality can be obtained at the growth temperature of 1450 ℃.

Arrays of Quasi-One-Dimensional GaAs Nanocrystals Grown on the Oxidized Surface of the Si/GaAs(001) Heterostructure: Effect of the Si Epitaxial Layer on the Array Structure

Structures with arrays of planar and tilted quasi-one-dimensional GaAs nanocrystals have been grown on GaAs(001) substrates. An epitaxial silicon layer oxidized in air was used as a passivation coating. The amount of silicon deposited varied from structure to structure and was equivalent to 1, 2, 4, and 6 atomic layers. It has been found that in the case of a passivation layer based on silicon with a thickness of 1 atomic layer, an array of planar nanocrystals is formed, and in other cases, inclined quasi-one-dimensional nanocrystals. Nanocrystals are surrounded by crystallites, the shape, size, orientation, and distribution density of which change with the amount of silicon. The lowest density of crystallites was achieved with a silicon layer 6 atomic layers thick. Keywords: molecular-beam epitaxial, GaAs, Si, quasi-one-dimensional nanocrystals, vapour-liquid-crystal.

Массивы квазиодномерных нанокристаллов GaAs, выращенные на окисленной поверхности гетероструктуры Si/GaAs(001): влияние толщины эпитаксиального слоя Si на строение массива

Structures with arrays of planar and tilted quasi-one-dimensional GaAs nanocrystals have been grown on GaAs(001) substrates. An epitaxial silicon layer oxidized in air was used as a passivation coating. The amount of silicon deposited varied from structure to structure and was equivalent to 1, 2, 4, and 6 atomic layers. It has been found that in the case of a passivation layer based on silicon with a thickness of 1 atomic layer, an array of planar nanocrystals is formed, and in other cases, inclined quasi-one-dimensional nanocrystals. Nanocrystals are surrounded by crystallites, the shape, size, orientation, and distribution density of which change with the amount of silicon. The lowest density of crystallites was achieved with a silicon layer 6 atomic layers thick.

Reduction of White Spot Defects in CMOS Image Sensors Fabricated Using Epitaxial Silicon Wafer with Proximity Gettering Sinks by CH2P Molecular Ion Implantation.

Using a new implantation technique with multielement molecular ions consisting of carbon, hydrogen, and phosphorus, namely, CH2P molecular ions, we developed an epitaxial silicon wafer with proximity gettering sinks under the epitaxial silicon layer to improve the gettering capability for metallic impurities. A complementary metal-oxide-semiconductor (CMOS) image sensor fabricated with this novel epitaxial silicon wafer has a markedly reduced number of white spot defects, as determined by dark current spectroscopy (DCS). In addition, the amount of nickel impurities gettered in the CH2P-molecular-ion-implanted region of this CMOS image sensor is higher than that gettered in the C3H5-molecular-ion-implanted region; and this implanted region is formed by high-density black pointed defects and deactivated phosphorus after epitaxial growth. From the obtained results, the CH2P-molecular-ion-implanted region has two types of complexes acting as gettering sinks. One includes carbon-related complexes such as aggregated C-I, and the other includes phosphorus-related complexes such as P4-V. These complexes have a high binding energy to metallic impurities. Therefore, CH2P-molecular-ion-implanted epitaxial silicon wafers have a high gettering capability for metallic impurities and contribute to improving the device performance of CMOS image sensors. (This manuscript is an extension from a paper presented at the 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM 2022)).

Effect of Gradient Doping on Charge Collection Efficiency of EBCMOS Devices

We investigated the effect of different gradient doping methods on the charge collection efficiency of the electron multiplication layer of EBCMOS devices. Exponential doping of the electron multiplication layer can form a built-in electric field in the electron multiplication layer that is favorable for photoelectron transport, so exponential doping instead of uniform doping in the electron multiplication layer of EBCMOS can effectively improve the charge collection efficiency. It is shown that exponential heavy doping on the side of the electron multiplication layer near the dead layer and exponential light doping on the side near the depletion region can improve the built-in electric field structure and increase the lifetime of the multiplied electrons, thereby improving the charge collection efficiency of EBCMOS. The optimized device achieves a charge collection efficiency of 94.48% at an incident electron energy of 4 keV, an electron beam diameter of 20 nm, a dead layer thickness of 60 nm, and a P-type silicon epitaxial layer thickness of 10 μm.

Automatic Defect Detection in Epitaxial Layers by Micro Photoluminescence Imaging

The early in-line detection of defects is a fundamental step in semiconductor manufacturing to ensure the device quality. Inspection techniques currently available can effectively detect large epitaxial defects causing morphological surface variations like stacking faults, while dislocations go undetected. Herein we introduce a new technology with enhanced machine learning analysis, based on contactless and non-destructive room temperature micro-photoluminescence imaging (micro-PL), for the detection and classification of defects in silicon epitaxial layers. With laboratory microscopy techniques we investigate the correspondence between different defect morphologies in micro-PL images and extended crystallographic defects. A good matching in terms of defect density is found between automatic micro-PL analysis and the standard laboratory analysis in an interval spanning from few defects/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> defects/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

High-performance germanium avalanche photodetector for 100 Gbit/s photonics receivers.

A high-bit rate and low-bias voltage waveguide-integrated vertical germanium avalanche photodetector is reported with doping optimization. This scheme alleviates the necessity of complex epitaxial single-crystal silicon layer and multiple ion implantation schemes. The optical absorption and carrier avalanche multiplication gain occur in the same germanium layer. The maximum gain is estimated to be 112.4 at an input power of -30.2dBm. With the input optical power of -16.1dBm, the gain-bandwidth product of nearly 141 GHz is obtained at 7.8 V bias. Meanwhile, a 4.6 dB sensitivity improvement for 60 Gbit/s signal reception is demonstrated with an avalanche gain of 5.1 at a soft-decision forward-error correction threshold (SD-FEC), i.e., bit-error-rate of 2×10-2. The absolute sensitivities of photonics receivers are -21, -18.6, -15.9, and -11.5dBm for 40, 60, 80, and 100 Gbit/s non-return-to-zero signals at the SD-FEC threshold. These demonstrated characteristics enable the reliable and robust on-chip photodetection for energy efficienct silicon photonic interconnects in the future.

Assessment of Surface Preparation Methods for Mercury (Hg) Probe Schottky Capacitance-Voltage (MCV) on Epitaxial Silicon

Mercury probe (Hg-probe) Schottky capacitance-voltage (CV) is widely used for carrier density and resistivity profiling in silicon epitaxial layers. Preparation of the silicon surface is crucial for obtaining high-quality CV measurements. There are a variety of methods currently being used to treat bare silicon epitaxial and polished bulk surfaces in preparation for Hg-Schottky CV measurements. The treatments include wet chemical and dry treatments. Usually, the treatment can be the limiting factor for both the measurement time and quality. In this evaluation, a number of typical treatments are evaluated for P-Type Epitaxial silicon surfaces. A novel concept for treating surfaces has also been investigated, which involves placing a silicon wafer in a chamber where it is exposed to a thermal and optimized ambient. This pretreatment chamber is referred to as PTC. A physics-based assessment of the typical P-type silicon surface treatments is made and presented.

Investigation of Vth Distribution Tails of Ground-Select-Line Cells and Edge Dummy Cells in a 3-D NAND Flash Memory

The threshold voltage ( Vth) distributions of ground-select-line (GSL) cells and edge dummy (DMY0) cells in a 3-D NAND flash memory are investigated. We characterize the Vth distributions in 3-D NAND flash samples with different fabrication processes and bitline voltages. Large DMY0 and GSL Vth distribution tails are observed in certain fabrication process and operation voltage conditions. The DMY0 Vth tail is attributed to a random distribution of grain boundary (GB) traps in a poly-silicon channel between GSL and DMY0. The GSL Vth tail is affected by ion implant energy in an epitaxial silicon layer underneath a GSL. A 3-D TCAD simulation is performed to study the effects of a GB trap position and a bitline voltage on the Vth distribution of DMY0. The influence of an implant dose profile in the epitaxial silicon on the GSL Vth distribution is also analyzed by 3-D simulation. The GSL and the DMY0 Vth distributions can be significantly improved by optimizing a fabrication process and choosing an appropriate bitline voltage.

Real-time monitoring of surface passivation of crystalline silicon during growth of amorphous and epitaxial silicon layer

Surface passivation of crystalline silicon (c-Si) is experimentally studied during the growth of a hydrogenated amorphous silicon (a-Si:H) and epitaxial silicon (epi-Si) passivation layer at a subnanometer to nanometer scale. The property of surface passivation is monitored in real time via in situ measurement of a photocurrent in c-Si under plasma-enhanced vapor deposition for the passivation layer growth. The measurement results suggest the following. Passivation is improved by the growth of an a-Si:H layer, where a large band offset is formed at the a-Si:H/c-Si interface, and the carrier recombination is suppressed. On the other hand, passivation is deteriorated with the growth of an ultrathin epi-Si layer (d≲2.5±1.0 nm) because the band offset is not formed at the interface, and plasma-induced defects are created in c-Si. However, passivation is improved with a thick epi-Si layer (d≳2.5±1.0 nm), where the band bending is formed near the epi-Si/c-Si interface, which partially suppresses the carrier recombination. The suppression of the plasma-induced defects as well as the formation of the band offset are important for surface passivation.

Large-area synthesis of a semiconducting silver monolayer via intercalation of epitaxial graphene

Two-dimensional monolayers consisting of a single element have attracted considerable interest due to their intriguing properties, which can be fundamentally different from the bulk counterparts. However, their large-scale synthesis often remains challenging owing to the nonlayered nature of the respective bulk crystal structures. In this Rapid Communication we show that the noble metal silver can be confined into the monolayer limit via intercalation between silicon carbide and epitaxial buffer layer graphene. Using angle-resolved photoelectron spectroscopy we reveal the formation of a silver-related valence band whose dispersion can be described by a simple, triangular-lattice tight-binding model. Interestingly, the synthesized silver monolayer is semiconducting as opposed to the prototype $sp$ bulk metal. The intercalation process further yields an $n$-type doped quasi-free-standing graphene monolayer, thereby realizing a two-dimensional metal/semiconductor heterostructure. Our results demonstrate the potential of epitaxial graphene on silicon carbide as a functional platform for the wafer-scale synthesis of monoelemental monolayers with unique attributes.

Formation and thermoelectric properties of the n- and p-type silicon nanostructures with embedded GaSb nanocrystals

A silicon heterostructure with four layers of embedded gallium antimonide nanocrystals was formed on a Si(111) substrate by co-deposition of Ga and Sb using solid-phase epitaxy. Si(111)2 × 1-Sb surface reconstruction formed prior to the GaSb nanocrystal growth, which kept the nanocrystals from decomposition during the silicon epitaxial layer formation. P- and n-type structures were obtained using silicon of different conductivity types. In the 200–550 K temperature range they showed increases in both electrical conductivity and Seebeck coefficient compared with the bulk samples, which was explained by the peculiarities of the heterointerface band alignment and density of states at the Fermi level. The results open the way for creating multilayer structures with enhanced thermoelectric performance.

A Mask Based on a Si Epitaxial Layer for the Self-Catalytic Nanowire Growth on GaAs(111)B and GaAs(100) Substrates

GaAs nanowires (NWs) were generated on the surface of GaAs(111)B and GaAs(100) substrates from molecular fluxes by the self-catalytic growth method. A mask for NW growth was fabricated by oxidizing the epitaxial silicon layer that was grown on a substrate surface by the molecular beam epitaxy (MBE) method. Silicon was oxidized in purified air without moving the structures out of the vacuum system of the MBE apparatus. The process of Si/GaAs heterostructure oxidation was investigated using single-wave and spectral ellipsometry. The oxidized silicon surface morphology was studied by the atomic force microscopy methods. The scanning electronic microscopy method was used to examine the samples with NWs. The NW density was about 2.6 × 107 and 3 × 107 cm–2 for (111)B and (100), respectively.

Electrical characterization of low temperature plasma epitaxial Si grown on highly doped Si substrates

Epitaxial silicon layers were grown on highly doped c-Si substrates using the plasma-enhanced chemical vapour deposition process (PECVD) at low temperature (175 °C). The transport and defect-related properties of these epi-Si layers were characterized by current density-voltage (J–V) and capacitance–voltage (C–V) techniques. The results show that the epi-Si layers exhibit a non-intentional n-type doping with a low apparent doping density of about 2 × 1015 cm−3. The admittance spectroscopy technique is used to investigate the presence of deep-level defects in the structure. An energy level at 0.2 eV below the conduction band has been found with a density in the range of 1015 cm−3 which may explain the observed apparent doping profile.

Маска на основе эпитаксиального слоя Si для самокаталитического роста нитевидных нанокристаллов на подложках GaAs (111)B и (100)

GaAs nanowire (NW) self-catalyzed growth on GaAs (111) B and GaAs (100) substrates was carried out by molecular beam epitaxy. A mask for the self-catalyzed NW growth was created by oxidizing an epitaxial silicon layer grown on the GaAs surface by molecular beam epitaxy (MBE). Silicon oxidation was realized in an atmosphere of purified air under normal conditions without moving the structures out from the vacuum system volume of the molecular beam epitaxy chamber. The oxidation process of a silicon layer was studied using single-wave and spectral ellipsometry and the surface morphology of oxidized silicon was studied by atomic force microscopy. Substrates with NWs were studied by scanning electron microscopy. The NW density was demonstrated to be 2.6•107 cm-2 and 3•107 cm-2 for (111)B and (100), respectively.

Annealing of Boron-Doped Hydrogenated Crystalline Silicon Grown at Low Temperature by PECVD.

We investigate low-temperature (<200 °C) plasma-enhanced chemical vapor deposition (PECVD) for the formation of p–n junctions. Compared to the standard diffusion or implantation processes, silicon growth at low temperature by PECVD ensures a lower thermal budget and a better control of the doping profile. We previously demonstrated the successful growth of boron-doped epitaxial silicon layers (p+ epi-Si) at 180 °C. In this paper, we study the activation of boron during annealing via dark conductivity measurements of p+ epi-Si layers grown on silicon-on-insulator (SOI) substrates. Secondary Ion Mass Spectroscopy (SIMS) profiles of the samples, carried out to analyze the elemental composition of the p+ epi-Si layers, showed a high concentration of impurities. Finally, we have characterized the p+ epi-Si layers by low-temperature photoluminescence (PL). Results revealed the presence of a broad defect band around 0.9 eV. In addition, we observed an evolution of the PL spectrum of the sample annealed at 200 °C, suggesting that additional defects might appear upon annealing.