Silicon Carbide Power MOSFETs Research Articles

Modelling for Multiport Converter-based Hybrid Power supply for Renewable Energy Source Application

This research work deals with the design, modeling and technical evaluation of multiport modular converter based hybrid Power supply using solar PV for small village. The village’s maximum power demand is 50kvA, consisting of demands of twenty (20) households. The first converter in the proposed multiport system is a high frequency isolated DC-DC converter fed with HVDC link yielding an output voltage of 700vDC. The isolated DC-DC converter uses a medium frequency transformer with primary and secondary side converters in input-series output-parallel (ISOP) configuration. Also, the output of first converter is connected to a solar PV and battery system through a buck-boost converter. The second converter in the system is solar PV fed three phase modular inverter designed to have output AC line voltage of 0.415 kV. The three phase inverter is based on modular multilevel converter (MMC) with interleaved modulation techniques. A silicon carbide power MOSFETs, with model numbers CPM3-10000-0270(CREE) and SD11703 (Solitron) are used as a building blocks for isolated DC-DC converter. On the other hand, SiC -MOSFET with part number SCT3017AL (RHOM) is used as basic building block for modular inverter. A solar PV module with open circuit voltage of 85V and maximum power rating of 415W is used to feed the inverter. Different scenarios such as changes in load and changes in solar irradiance are used for critically evaluating the performances of the system under question. The output voltage THD, current distortions, changes in the converter output voltage, current magnitude and converter efficiency are used for performance evaluation of the system under consideration. Simulink/ PLECS (Piecewise Linear Electrical Circuit Simulation) combo simulation platform is used to model and simulate the system in question. Simulation results showed that the proposed multiport converter system can be a viable alternative to low frequency distribution transformer.
 Keywords: Multiport converter, MMC, DC-DC converter, Hybrid power Supply, Solar PV.

(Invited) Design of Surface Oxidation and Nitridation Reactions on 4H-SiC for the Advanced SiC Gate Stack Formation Processes

Silicon carbide (SiC) MOSFETs are expected to replace Si bipolar transistors partially in applications such as automotive, railroad, and other high-voltage applications. But the resistance of the MOS inversion layer channel limits the performance of MOSFETs. It has been clarified that the effective carrier density in the inversion channel is significantly reduced by the carrier trapping by the high density of defect states distributed nearby SiO2/SiC interface. In this study, our understanding of oxidation and nitridation reactions of SiC for designing the gate stack formation processes to improve the MOS interface characteristics is presented.Choosing SiO2 as a gate dielectric for SiC is favorable from various aspects including its ability to form a thermodynamically stable interface with SiC, which is free of reactions at the process temperature. However, from a microscopic point of view, Si-O bond alone cannot cover the whole surface of SiC and the excess C atoms on the surface causes the formation of defect states. One of the possible approaches has been employing an appropriate thermal oxidation condition to enhance the excess carbon elimination by forming CO. For example, we have experimentally demonstrated a significant reduction of Dit by employing high-temperature thermal oxidation with a rapid heating furnace [1]. However, such approach seems to bring a serious drawback such as defect formation in the surface region of SiC, experimentally detected by a lattice distortion in the beneath of SiO2 after high-temperature oxidation [2]. One of the possible reasons for such deterioration would be an invasion of activated oxygen atoms into the surface region of SiC [3]. A possible approach to avoid such drawback of high-temperature oxidation process would be utilizing H2O vapor for the formation of SiO2/SiC interface at relatively lower temperature while avoiding the damages on SiC surface [4], since H2O oxidation was found to be advantageous to remove CO more efficiently than O2 oxidation even at low temperature.On the other hand, another approach to passivate SiC surface is the surface nitridation technique, which is the most common way in industry to fabricate SiC MOS interface typically achieved by high-temperature annealing in NO gas [5]. Nitridation can replace the topmost C sites with N without inducing significant distortion in the SiC surface structure, to suppress the C-related defect formation at the interface. The advantage of this reaction is that it proceeds self-limited manner and N atoms are introduced only on the topmost surface of SiC. Note that NO gas triggers the surface nitridation by removing the surface C atoms in the form of CO by oxidation. Actually, a very similar reaction occurs even when SiC is annealed in N2 [6] ambient with a slight addition of O2. We experimentally found that the surface N density saturated with different values when we employed various N2+O2 atmosphere with different O2 concentration. Therefore we setup a simple model to describe the saturation behavior, which is determined by the balance between the rate of N uptake (N+) and the rate of N desorption (N‒) mainly due to the oxidation reaction [7]. This model was found to represent the time-dependent change of surface N density well, by assuming that N+ remained constant during the reaction and N‒ was proportional to both the reaction rate of interface oxidation and the surface N density [8]. Based on this simplified model, it is possible to design a process to tune the N density. By choosing appropriate temperature and oxygen partial pressure we can increase N density at the surface to minimize the interface trap density. Further improvement of surface N density would be achieved by further controlling of the blance between N uptake and N desorption reactions.As we have discussed so far, the role of materials science to clarify the interface phenomena is significantly important to achieve a further improved SiC MOS interface characteristics for the next generation SiC power MOSFET process technology. [1] R. Kikuchi and K. Kita, Appl. Phys. Lett. 105, 032106 (2014).[2] A. D. Hatmanto and K. Kita, Appl. Phys. Express 11, 011201 (2018).[3] A. D. Hatmanto and K. Kita, Jpn. J. Appl. Phys. 59, SMMA02 (2020).[4] H. Hirai and K. Kita, Appl. Phys. Lett. Appl. Phys. Lett. 113, 172103 (2018).[5] J. Rozen et al., J. Appl. Phys. 105, 124506 (2009).[6] A.Chanthaphan et al., AIP Adv. 5, 097134 (2015).[7] T. Yang and K. Kita, Jpn. J. Appl. Phys. 61, SC1077 (2022).[8] T. Yang and K. Kita, SSDM 2023, Chiba.

Reliable development of an IMS-based SiC power module

This paper presents the design for performance and reliability of a low inductance high switching frequency silicon carbide power MOSFET bi-directional switch. The design relies on insulated metal substrate technology and includes in-depth thermal analysis. The switch prototype is validated on the basis of preliminary functional and reliability investigations, including power cycling.

Life-cycle energy demand comparison of medium voltage Silicon IGBT and Silicon Carbide MOSFET power semiconductor modules in railway traction applications

Power semiconductors process roughly 70 % of global energy, with a higher percentage expected as worldwide transport electrification, renewables and wide-band-gap (WBG) semiconductors are implemented, significantly affecting global energy savings. This manuscript evaluates the cumulative energy demand (CED) encompassing the manufacture and use-phase in a railway traction application of silicon (Si) and silicon carbide (SiC) power semiconductor modules. Realistic manufacturing data from a power semiconductor fab has been considered for 3.3 kV/450 A state-of-the-art Si and SiC LinPak modules. SiC devices presented around 2.6 – 3.8× higher CED per area than Si devices in the manufacturing phase. However, due to the considerably smaller SiC chip area per ampere required, a 1.1 – 1.6× lower grey energy than Si technology is estimated. For the first time, such analysis is based on specialized power semiconductor fab data for both technologies and provides a baseline for the life cycle energy assessment of power electronics systems. Besides, the use-phase energy losses were evaluated for a realistic railway application, considering an operational lifetime of 30 years. The module manufacturing energy is negligible compared to the use-phase stage. Furthermore, the SiC technology presented an estimated energy-saving potential of 24 MWh/lifetime per module compared to the Si device.

Proton Irradiation-Induced Reliability Degradation of SiC Power MOSFET

The effect of 53 MeV proton irradiation on the reliability of silicon carbide power MOSFETs was investigated. Post-irradiation gate voltage stress was applied and early failures in time-dependent dielectric breakdown (TDDB) test were observed for irradiated devices. The applied drain voltage during irradiation affects the degradation probability observed by TDDB tests. Proton-induced single event burnouts (SEB) were observed for devices which were biased close to their maximum rated voltage. The secondary particle production as a result of primary proton interaction with the device material was simulated with the Geant4-based toolkit.

Silicon Carbide Power Devices: Progress and Future Outlook

Silicon Carbide (SiC) power devices have become commercialized and are being adopted for many applications after 40 years of effort to produce large diameter wafers and high performance device structures. This paper provides a historical perspective of the key breakthroughs that were needed to make progress towards this goal. The JBS rectifier concept was a critical innovation required to make SiC power Schottky rectifiers viable. The Baliga-Pair or Cascode concept was an intermediate step to realize a practical SiC power switch in the 1990s. An essential unique innovation created in the 1990s was the shielded planar SiC power MOSFET structure that is now commonly used for commercial products. Shielded trench-gate SiC power MOSFETs were also proposed in the 1990s which led to commercial products in the last 5 years. Although achieving a low specific on-resistance in SiC power MOSFETs was essential at the inception of the technology, its penetration into power electronics applications is now driven by performance metrics for high frequency circuits. Device structural enhancements to improve the high frequency figures-of-merit are described that have led to major strides in performance. This includes the JBSFET concept where a JBS diode is integrated into the MOSFET structure to suppress current flow through the body diode; the SG and BG MOSFET structures which reduce the gate-drain charge; and the OCTFET structure where the gate-drain overlap area is reduced. Future developments in SiC power devices include increasing the blocking voltage rating to expand the applications spectrum. In addition, a SiC monolithic bi-directional switch has been demonstrated to allow implementation of matrix converters; and a SiC monolithic reverse blocking switch has been demonstrated to allow deployment of current source inverters.

Autonomous Electric Race Car Inverter Development: Revving up the future with resource efficient drive technology

As the electric drive finds its way progressively into important industry sectors like mobility, transportation, agriculture, production, and supporting services, it becomes increasingly important to have individually optimized technical solutions for the manifold applications. Therefore, a high number of engineers with interdisciplinary competencies will be needed soon to comply with the demand of the worldwide markets. A key component for an often-used variant of the electric drivetrain is the full-bridge inverter, which is subject to a wide spectrum of different requirements. In 2021, the University of Denver (DU), started a cooperation with the University of Applied Sciences Augsburg (UASA) to develop a full-bridge inverter for an autonomous, electrical Formula Student race car, using four permanent magnet synchronous machines as an all-wheel drive. To improve the performance of the race car, the inverter must be lightweight, package optimized, electromagnetic compatibility compliant, safe, and reliable when it distributes a maximum of 80 kW instantaneous power from the battery at a voltage between 420 V and 600 V individually to the four wheels. This article documents the inverter development process using silicon carbide MOSFET power modules, with the goal of using future results in the race car and the knowledge transfer for the education of engineering students. This transatlantic partnership between DU and UASA also serves as a success story for intercontinental collaborative development based on modern communication and decentralized development techniques.

Impact of Temperature on Neutron Irradiation Failure-in-Time of Silicon and Silicon Carbide Power MOSFETs

Accelerated neutron tests on silicon (Si) and silicon carbide (SiC) power MOSFETs at different temperatures and drain bias voltages were performed at the ChipIr facility (Didcot, UK). A super-junction silicon MOSFET and planar SiC MOSFETs with different technologies made by STMicroelectronics were used. Different test methods were employed to investigate the effects of temperature on neutron susceptibility in power MOSFETs. The destructive tests showed that all investigated devices failed via a single-event burnout (SEB) mechanism. Non-destructive tests conducted by using the power MOSFET as a neutron detector allowed measuring the temperature trend of the deposited charge due to neutron interactions. The results of the destructive tests, in the −50 °C–180 °C temperature range, revealed the lack of a common trend concerning the FIT temperature dependence among the investigated SiC power MOSFETs. Moreover, for some test vehicles, the FIT-temperature curves were dependent on the bias condition. The temperature dependence of the FIT values, observed in some SiC devices, is weaker with respect to that measured in the Si MOSFET. The results of the non-destructive tests showed a good correlation between the temperature trends of the deposited charge with those of FIT data, for both Si and SiC devices.

A Highly Integrated Multichip SiC MOSFET Power Module With Optimized Electrical and Thermal Performances

This paper proposes a highly integrated multichip silicon carbide (SiC) MOSFET power module packaging with optimized electrical and thermal performances. The structure of the module is to stack the two power switches up and down with the cooling system and the decoupling circuit integrated inside the module. The structural characteristics of the module realize the co-optimization of the switching performance, thermal management, and electromagnetic interference (EMI) issue of the multichip SiC module, which effectively solve the contradiction in the optimization of the electrical and thermal performance. In addition, by optimizing the process flow and designing a variety of soldering fixtures, the feasibility of the process and the engineering margin is increased. Experiments and simulations show that the proposed SiC power module has good electrical and thermal performance. The loop parasitic inductance is reduced to 2.02 nH and the common-mode (CM) current is eliminated. The drain–source voltage overshoot during the turn-off transient is reduced by 76.5%, and the voltage oscillation is significantly improved due to the integration of the decoupling circuit. At the same time, the integrated liquid-cooling heatsink greatly improves the cooling efficiency of the module on the premise of ensuring the insulation performance of the module.

Gate Oxide Degradation Condition Monitoring Technique for High-Frequency Applications of Silicon Carbide Power MOSFETs

Gate oxide degradation, which considerably affects turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> /- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> dynamics of the switch, embraces a large percentage of chip-related failure modes both in silicon and silicon carbide power MOSFETs. The gate oxide layer is thinner in silicon carbide power MOSFETs in comparison to their silicon-based counterparts. Consequently, the problem of gate oxide degradation has become a more crucial impediment in achieving reliable performance in silicon carbide power MOSFETs. This problem is even more severe in high-frequency applications due to higher EMI signature and complicated and costly measurement. In this article, a reliable fully analog cost-effective gate oxide degradation condition monitoring technique is proposed and validated. High-order harmonics magnitudes of drain–source voltage are used to produce a dc signal as the aging precursor of the gate oxide region. Using a dedicated degradation setup, the credibility of the developed condition monitoring technique was examined at different rates of gate oxide degradation for 650-V/22-A silicon carbide discrete MOSFET. In 200-kHz, 217-V switch operation, the proposed precursor showed 68% change in comparison to its initial value. This brings a high-resolution assessment on the reliability level of the switch gate oxide region.

Wireless Control of Active Gate Drivers for Silicon Carbide Power MOSFETs

Wireless Control of Active Gate Drivers for Silicon Carbide Power MOSFETs

A compact circuit-level model for single-event burnout in SiC power MOSFET devices

This paper presents a compact circuit-level model for single-event burnout (SEB) in silicon carbide (SiC) metal-oxide field-effect transistors (MOSFETs). Key parameters of the equivalent circuit model of the MOSFET are analyzed and determined in detail, including nonlinear parasitic drain-source capacitance and nonlinear parasitic gate-drain capacitance. The effect of the parasitic bipolar junction transistor is considered and an iteratively optimized double-exponential current source is used to simulate the transient power current generated by incident heavy ions. The equivalent circuit model of the MOSFET is verified by comparing the SPICE simulation curves, TCAD simulation curves, and the curves in the SiC power double trench MOSFET’s datasheet (SCT3080KL). Then, the SEB is caused by heavy ions at various incident positions, linear energy transfer values, drain-source voltage (V ds), and gate-source voltage (V gs) using the TCAD and HSPICE simulations. Simulation results on the SPICE model coincide with the TCAD simulation results. Moreover, this compact model is used to predict the SEB threshold for devices with higher breakdown voltage ratings.

Condition monitoring indicators for Si and SiC power modules

The reliability of power modules plays a crucial role in developing safer and smarter generations of electric vehicles. Condition monitoring represents a possible solution to predict the possible occurrence of catastrophic failures and avoid unexpected breakdowns. More specifically, power modules for inverter applications are a technology requiring condition monitoring indicators to detect ongoing degradation mechanisms. In this work, both silicon IGBT and silicon carbide MOSFET power modules are thermally stressed through the application of a pulsed direct current until reaching end-of-life limits. As a result, two main failure mechanisms occurring at package level are observed: chip solder degradation and bond-wire damages. In addition, on-state voltage, junction temperature, and thermal resistance are measured during the power cycling as parameters to monitor the device states of health. After the test, the chip solder conditions and bond-wires robustness are checked through scanning acoustic microscope images and optical inspections, respectively. The novelty of this work lies in refining and comparing health indicators for silicon and silicon carbide power modules.

Gate Capacitance Characterization of Silicon Carbide and Silicon Power mosfets Revisited

Capacitance–voltage (C–V) gate characteristics of power metal-oxide-semiconductor field-effect transistors ( <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s) play an important role in the dynamic device performance. C–V characterization of the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> gate structure is a necessary step for evaluating the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> switching behavior and calibrating lumped equivalent capacitances of <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> compact models. This article presents a comprehensive analysis on gate C–V measurements of silicon (Si) and silicon carbide (SiC) power <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s leading to clear measurement guidelines. The requirements on the measurement setup, the selection of equivalent models used for the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> capacitance extraction, and the measurement frequency range are defined and supported by an accurate C–V characterization of several Si- and SiC power <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s. The results show that the gate-source and gate-drain capacitances should be extracted at a frequency of some 10 kHz rather than at 1 MHz, as typically adopted in datasheets, to avoid parasitic effects introduced by the measurement setup and package. Furthermore, analytical expressions for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$C_\text{dg}$</tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$C_\text{sg}$</tex-math></inline-formula> were derived based on a lumped equivalent circuit, which explain the influence of the measurement setup and the package parasitics on the C–V measurements. Nonideal measurement conditions are identified and correlated to the differences in C–V extraction with either parallel or series-equivalent model. A new method is proposed to estimate the ratio of the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> ’s <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state resistance components <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$R_\text{ch}$</tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$R_\text{drift}$</tex-math></inline-formula> based on the presented C–V measurement guidelines, which are applicable to all three- and four-terminal power <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s.

A Critical Review on Reliability and Short Circuit Robustness of Silicon Carbide Power MOSFETs

A Critical Review on Reliability and Short Circuit Robustness of Silicon Carbide Power MOSFETs

Review of Methodologies for Evaluating Short-Circuit Robustness and Reliability of SiC Power MOSFETs

To accelerate the broad application of silicon carbide (SiC) power MOSFETs, their short-circuit (SC) robustness and reliability must be thoroughly evaluated. This article, therefore, presents an overview of related research methods aiming to meet that objective. Topics reviewed include non-destructive tester (NDT) used to implement SC faults, extraction and analysis of degradation parameters, and failure analysis of SiC MOSFETs. Concerning NDT, its design criteria and methods for evaluating SC robustness are discussed. Then, the key parameters used to assess SC reliability and methods for investigating degradation mechanisms are discussed and summarized. Finally, failure analysis techniques and their contributions to failure mechanisms are reviewed.

Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique

In this article, the design, fabrication and characterization of silicon carbide (SiC) complementary-metal-oxide-semiconductor (CMOS)-based integrated circuits (ICs) are presented. A metal interconnect strategy is proposed to fabricate the fundamental N-channel MOS (NMOS) and P-channel MOS (PMOS) devices that are required for the CMOS circuit configuration. Based on the mainstream 6-inch SiC wafer processing technology, the simultaneous fabrication of SiC CMOS ICs and power MOSFET is realized. Fundamental gates, such as inverter and NAND gates, are fabricated and tested. The measurement results show that the inverter and NAND gates function well. The calculated low-to-high delay (low-to-high output transition) and high-to-low delay (high-to-low output transition) are 49.9 and 90 ns, respectively.

An Overview about Si, Superjunction, SiC and GaN Power MOSFET Technologies in Power Electronics Applications

This work presents a comparative analysis among four power MOSFET technologies: conventional Silicon (Si), Superjunction (SJ), Silicon Carbide (SiC) and Gallium Nitride (GaN), indicating the voltage, current and frequency ranges of the best performance for each technology. For this, a database with 91 power MOSFETs from different manufacturers was built. MOSFET losses are related to individual characteristics of the technology: drain-source on-state resistance, input capacitance, Miller capacitance and internal gate resistance. The total losses are evaluated considering a drain-source voltage of 400 V, power levels from 1 kW to 16 kW (1 A–40 A) and frequencies from 1 kHz to 500 kHz. A methodology for selecting power MOSFETs in power electronics applications is also presented.

Cu Clip-Bonding Method With Optimized Source Inductance for Current Balancing in Multichip SiC MOSFET Power Module

Cu clip-bonding is a promising packaging method for lower resistance, lower inductance, and higher reliability than wire-bonding. Previous studies only simply replace bond wires with Cu clips on an individual die. However, current sharing and thermal coupling issues among multichip modules are still big challenges in the clip-bonded silicon carbide (SiC) <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> power module. In this article, a novel source inductance optimization method is proposed. Extra modification paths (MPs) on Cu clips are used in this method. A clip-bonded half-bridge multichip SiC power module is designed and fabricated to verify the superiority of the method. In a simple straight layout, the distance between adjacent dies is large enough to avoid heat concentration and junction temperature differences resulting from the thermal coupling effect. The MPs structure on the Cu clip is designed to optimize the power source inductances. Parasitic circuit model and mathematical analysis are derived to demonstrate the features of proposed MPs. Simulations and experiments workbench are conducted to analyze drain current sharing performance. Derivation and simulation show the highest branch's inductance is reduced. Test results show the current imbalance and loss imbalance are relatively mitigated, which proves that the effect of power inductances imbalance is suppressed by the proposed optimization method.

Synergistic Effect of Electrical Stress and Neutron Irradiation on Silicon Carbide Power MOSFETs

The synergistic effect of radiation and bias voltage for the commercial silicon carbide (SiC) power MOSFETs was investigated by 14-MeV neutron irradiation in this article. The types of C3M0065090D and C2M0080120D commercial SiC power MOSFETs from CREE studied in this article show consistent changes after the 14-MeV neutron irradiation. The results show that the devices biased during irradiation experienced more degradation than that only irradiated and biased devices. Compared with the devices only irradiated and biased, the devices biased during irradiation experienced an additional decrease in saturation current and a further decrease in peak transconductance. The defects in the devices were characterized by the low-frequency noise (LFN) and deep-level transient spectrum (DLTS) methods. The results show that the synergistic effect increased the defect concentration of the device, resulting in further degradation of the electrical performance of the device compared to the control group without a bias voltage. The defect characterization shows that the drain&#x2013;source voltage leads to the accumulation of carbon and silicon vacancies induced by irradiation at the interface, which results in intensified radiation damage and significant changes in the performance of the device at low neutron fluence.