(Invited) Design of Surface Oxidation and Nitridation Reactions on 4H-SiC for the Advanced SiC Gate Stack Formation Processes

Abstract

Silicon carbide (SiC) MOSFETs are expected to replace Si bipolar transistors partially in applications such as automotive, railroad, and other high-voltage applications. But the resistance of the MOS inversion layer channel limits the performance of MOSFETs. It has been clarified that the effective carrier density in the inversion channel is significantly reduced by the carrier trapping by the high density of defect states distributed nearby SiO2/SiC interface. In this study, our understanding of oxidation and nitridation reactions of SiC for designing the gate stack formation processes to improve the MOS interface characteristics is presented.Choosing SiO2 as a gate dielectric for SiC is favorable from various aspects including its ability to form a thermodynamically stable interface with SiC, which is free of reactions at the process temperature. However, from a microscopic point of view, Si-O bond alone cannot cover the whole surface of SiC and the excess C atoms on the surface causes the formation of defect states. One of the possible approaches has been employing an appropriate thermal oxidation condition to enhance the excess carbon elimination by forming CO. For example, we have experimentally demonstrated a significant reduction of Dit by employing high-temperature thermal oxidation with a rapid heating furnace [1]. However, such approach seems to bring a serious drawback such as defect formation in the surface region of SiC, experimentally detected by a lattice distortion in the beneath of SiO2 after high-temperature oxidation [2]. One of the possible reasons for such deterioration would be an invasion of activated oxygen atoms into the surface region of SiC [3]. A possible approach to avoid such drawback of high-temperature oxidation process would be utilizing H2O vapor for the formation of SiO2/SiC interface at relatively lower temperature while avoiding the damages on SiC surface [4], since H2O oxidation was found to be advantageous to remove CO more efficiently than O2 oxidation even at low temperature.On the other hand, another approach to passivate SiC surface is the surface nitridation technique, which is the most common way in industry to fabricate SiC MOS interface typically achieved by high-temperature annealing in NO gas [5]. Nitridation can replace the topmost C sites with N without inducing significant distortion in the SiC surface structure, to suppress the C-related defect formation at the interface. The advantage of this reaction is that it proceeds self-limited manner and N atoms are introduced only on the topmost surface of SiC. Note that NO gas triggers the surface nitridation by removing the surface C atoms in the form of CO by oxidation. Actually, a very similar reaction occurs even when SiC is annealed in N2 [6] ambient with a slight addition of O2. We experimentally found that the surface N density saturated with different values when we employed various N2+O2 atmosphere with different O2 concentration. Therefore we setup a simple model to describe the saturation behavior, which is determined by the balance between the rate of N uptake (N+) and the rate of N desorption (N‒) mainly due to the oxidation reaction [7]. This model was found to represent the time-dependent change of surface N density well, by assuming that N+ remained constant during the reaction and N‒ was proportional to both the reaction rate of interface oxidation and the surface N density [8]. Based on this simplified model, it is possible to design a process to tune the N density. By choosing appropriate temperature and oxygen partial pressure we can increase N density at the surface to minimize the interface trap density. Further improvement of surface N density would be achieved by further controlling of the blance between N uptake and N desorption reactions.As we have discussed so far, the role of materials science to clarify the interface phenomena is significantly important to achieve a further improved SiC MOS interface characteristics for the next generation SiC power MOSFET process technology. [1] R. Kikuchi and K. Kita, Appl. Phys. Lett. 105, 032106 (2014).[2] A. D. Hatmanto and K. Kita, Appl. Phys. Express 11, 011201 (2018).[3] A. D. Hatmanto and K. Kita, Jpn. J. Appl. Phys. 59, SMMA02 (2020).[4] H. Hirai and K. Kita, Appl. Phys. Lett. Appl. Phys. Lett. 113, 172103 (2018).[5] J. Rozen et al., J. Appl. Phys. 105, 124506 (2009).[6] A.Chanthaphan et al., AIP Adv. 5, 097134 (2015).[7] T. Yang and K. Kita, Jpn. J. Appl. Phys. 61, SC1077 (2022).[8] T. Yang and K. Kita, SSDM 2023, Chiba.