Silicon Carbide Junction Field-effect Transistor Research Articles

Influence of Gate Depletion Layer Width on Radiation Resistance of Silicon Carbide Junction Field-Effect Transistors

Silicon carbide junction field-effect transistors (SiC JFETs) are promising candidates as devices applicable to radiation conditions, such as the decommissioning of nuclear facilities or the space environment. We investigate the origin of the threshold volage (Vth) shift and hysteresis of differently structured SiC JFETs. A large positive Vth shift and hysteresis are observed for a depletion-type JFET with a larger depletion layer width. With changing the sweep range of the gate voltage and depletion width, the Vth shift was positively proportional to the difference between the channel depth and depletion width (channel depth–gate depletion width). By illuminating the sub-band gap light, the Vth of the irradiated depletion JFETs recovers close to nonirradiated ones, while a smaller shift and hysteresis are observed for the enhancement type with a narrower width. It can be interpreted that positive charges generated in a gate depletion layer cause a positive Vth shift. When they are swept out from the depletion layer and trapped in the channel, this gives rise to a further Vth shift and hysteresis in gamma-irradiated SiC JFETs.

Cascaded SiC JFET Topology for High-Voltage Solid-State Circuit Breaker Applications

With evolving landscape of direct current (DC) power transmission and distribution, a reliable and fast protection against faults is critical. High performance DC solid-state circuit breakers (SSCBs) can be designed using silicon carbide (SiC) junction field-effect transistors (JFETs), which utilize the device's intrinsic normally-ON characteristic and low ON-resistance. However, for SSCB that require high-voltage (HV) blocking capability, a proper number of JFETs need to be connected in series to achieve the desired voltage blocking rating. It has been conventional to add a controlling normally-OFF transistor, such a metal-oxide-semiconductor field-effect transistor (MOSFET), resulting in a circuit with normally-OFF behavior. However, disparities both in the voltage rating and in the ON-resistance between MOSFETs and JFETs tend to complicate the circuit design, and physically, they may lead to serious localized thermal stresses. A significant challenge remains with ensuring equal voltage balancing across the JFETs during the switching transitions as well as the blocking stage as it is crucial to prevent permanent damages from over-voltage stresses. Therefore, this article presents a new switch topology, in which a cascaded JFET configuration is operated without using a control MOSFET or other added control device. The dynamic voltage balancing network to synchronize both the JFETs' turn ON and OFF intervals is described analytically. Moreover, a novel static voltage balancing network is proposed to establish equal sharing of the total blocking voltage across the series connection of JFETs while maintaining low power loss.

Gate Driver Circuit with All-Magnetic Isolation for Cascode-Connected SiC JFETs in a Three-Level T-Type Bridge-Leg

This article presents a gate driver circuit with all-magnetic isolation for driving silicon carbide (SiC) power devices in a three-level T-type bridge-leg. Gate driver circuitry for SiC devices has to be tolerant of rapid common-mode voltage changes. With respect to the resultant potentially problematic common-mode current paths, an arrangement of transformers is proposed for supplying the power devices with drive signals and power for their local floating gate driver circuits. The high-frequency carrier phase-switching technique is used to reduce the number of transformers. Signal timing and other implementation issues are addressed when using this arrangement with the T-type converter. The circuit is demonstrated in a 540 V bridge-leg constructed around 650 V and 1200 V cascode-connected normally-on SiC junction field effect transistors (JFETs).

A 60-MHz Silicon Carbide Voltage-Controlled Oscillator for Extreme Temperature Applications

In this brief, a custom-built silicon carbide (SiC) junction field-effect transistor (JFET) is characterized from room temperature to 52°C, and a 60 MHz voltage-controlled oscillator (VCO) based on this SiC JFET is designed and fabricated through low temperature co-fired ceramic (LTCC) process. The test results of the VCO prototype demonstrate that the proposed SiC JFET VCO is capable of operating from 25 °C to 500 °C. RF signal of 50dB above the noise floor is generated, and the tuning gain of 9.22 kHz/V is achieved at 500 °C. The proposed SiC JFET VCO can serve as the fundamental building block for wireless sensing or data communication in extreme temperature industrial and space applications.

A silicon carbide high gain differential amplifier for extreme temperature applications

In this paper, a high temperature, high gain differential amplifier based on a custom-built silicon carbide (SiC) N-channel junction field effect transistor (JFET) only, without using complementary P-channel devices is proposed. The operation principle of this active load differential amplifier is discussed, and the expression of the differential gain is derived. A prototype circuit is fabricated using thick film process on an alumina substrate and tested from room temperature up to 500 °C to demonstrate the high temperature capability of the proposed differential amplifier. The differential gain of 50.8 dB is achieved with 58.6 dB common-mode rejection ratio (CMRR) and 9.1 MHz gain bandwidth product (GBW) at 500 °C. Excellent linearity and low output impedance of the proposed differential amplifier are also demonstrated at various temperatures. The proposed SiC JFET high gain differential amplifier can serve as a fundamental building block of the signal conditioning circuitry to be integrated with the sensing element for extreme environment applications.

SiC Complementary Junction Field-Effect Transistor Logic Gate Operation at 623 K

Here, we show that silicon carbide (SiC) complementary logic gates composed of p- and n-channel junction field-effect transistors (JFETs) fabricated by ion implantation operate at 623 K with a supply voltage as low as 1.4 V. The logic threshold voltage shift of the complementary JFET (CJFET) inverter is only 0.2 V from 300 to 623 K. Furthermore, temperature dependencies of the static and dynamic characteristics of the CJFET inverter are well explained by a simple analytical model of SiC JFETs.

Silicon Carbide Junction Field Effect Transistor Compact Model for Extreme Environment Integrated Circuit Design

Abstract Presented is a temperature and geometry scalable 800°C Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) compact device model designed to simulate the small signal effects of the SiC JFET-R process developed by NASA Glenn Research Center. With the JFET-R process pushing the temperature limits of integrated circuits, a high-fidelity device model capable of predicting the performance over temperature and geometry is required to realize the thermal ruggedness this process provides. A high temperature (HT) packaging system was utilized to characterize a SiC JFET device up to 800°C with a dwell time of 9 hours during a single test. Invaluable device characterization data was obtained and utilized to extend the device model presented to simulate SiC JFET performance continuously over 800°C.

A Normally-off Copackaged SiC-JFET/GaN-HEMT Cascode Device for High-Voltage and High-Frequency Applications

A 1200-V/100-mΩ silicon carbide (SiC) junction field-effect-transistor (JFET)/ gallium nitride (GaN) high-electron-mobility-transistor (HEMT) hybrid power switch is demonstrated, which features a flip-chip copackaged cascode configuration incorporating a vertical SiC JFET and a lateral GaN-HEMT. The high-voltage SiC-JFET provides the high-voltage blocking capability while the low-voltage GaN-HEMT enables the normally- off gate control with superior switching characteristics. Compared to conventional SiC-JFET/Si- mosfet cascode devices, the SiC-JFET/GaN-HEMT cascode device exhibits fast switching speed, which has been validated by systematic characterizations including static/dynamic device-level measurements and board-level hard-switching tests. Meanwhile, the device is free from several notorious issues of high-voltage GaN power transistors such as dynamic on -state resistance degradation and threshold voltage shift. Such a wide-bandgap semiconductor-based hybrid switch is suitable to be deployed in high-power and high-efficiency power conversion systems.

Experimental Study on Short-Channel Effects in Double-Gate Silicon Carbide JFETs

Short-channel effects (SCEs) in double-gate silicon carbide junction field-effect transistors (JFETs) fully fabricated by ion implantation are experimentally investigated. The threshold voltage shift, drain-induced barrier lowering, and subthreshold slope degradation are clearly observed in the fabricated p- and n-JFETs. The SCEs are quantitatively evaluated by comparing with the theoretical values obtained by solving a 2-D Poisson equation, which shows good agreement with experiments. The dominant parameter for the SCEs in JFETs is the ratio of the channel length ( ${L}$ ) to the channel thickness ( ${a}$ ), and the device scaling rule to avoid the SCEs is estimated to be ${L}/{a} > {3}$ .

Short Circuit Fault Discrimination Using SiC JFET Based Self-Powered Solid State Circuit Breakers in a Residential DC Community Microgrid

This article identifies and validates the use of ultrafast silicon carbide (SiC) junction field effect transistor (JFET)-based self-powered solid-state circuit breakers (SSCBs) as the enabling protective device for a 340 Vdc residential dc community microgrid. These SSCBs will be incorporated into a radial distribution system in order to enhance fault discrimination through autonomous operation. Because of the nature and characteristics of short-circuit fault inception in dc microgrids, the time–current trip characteristics of protective devices must be several orders of magnitude faster than conventional circuit breakers. The proposed SSCBs detect short-circuit faults by sensing the sudden voltage rise between its two power terminals and draw power from the fault condition itself to turn off SiC JFETs and then, coordinate with no-load contacts that can isolate the fault. Depending upon the location of the SSCBs in the microgrid, either unidirectional or bidirectional implementations are incorporated. Cascaded SSCBs are tuned using a simple resistor change to enable fault discrimination between upstream high-current feeds and downstream lower current branches. Operation of one of the SSCBs and three in cascaded arrangements are validated both in simulation and with a hardware test platform. Thermal impact on the SSCB is discussed as well. The target application is a residential dc microgrid that will be installed as part of a revitalization effort of an inner city Milwaukee neighborhood.

Modelling of Dynamic Properties of Silicon Carbide Junction Field-Effect Transistors (JFETs)

The paper deals with the problem of modelling and analyzing the dynamic properties of a Junction Field Effect Transistor (JFET) made of silicon carbide. An examination of the usefulness of the built-in JFET Simulation Program with Integrated Circuit Emphasis (SPICE) model was performed. A modified model of silicon carbide JFET was proposed to increase modelling accuracy. An evaluation of the accuracy of the modified model was performed by comparison of the measured and calculated capacitance–voltage characteristics as well as the switching characteristics of JFETs.

Dynamic Voltage Balancing for the High-Voltage SiC Super-Cascode Power Switch

Presented in this paper is an optimization method to improve the dynamic performance of high-voltage super-cascode power switches (SCPSs) by implementing silicon carbide (SiC) junction field-effect transistor (JFET). The basic operating principle of SCPS is explained at the beginning of the paper. Equivalent circuit models are outlined next, with equations describing the voltage distribution among each SiC JFET during switching transients. Based on the sensitivity analysis, a component optimization method for balancing the SCPS internal voltage is proposed, which effectively eliminates the overvoltage. This significantly reduces the switching loss and the chance of diode avalanche. Compared with the nonoptimized case, the turn-on loss of the SCPS is reduced to 8.85%, and the turn-off loss reduces to 48.4%.

Analysis and Modeling of SiC JFET Bi-Directional Switches Parasitic Oscillation

Silicon carbide (SiC) junction field-effect transistor (JFET) based bi-directional switches (BDSs) have great potential in the construction of several power electronic circuits, including matrix converters, multi-level converters, solid state breakers, and so on. Parasitic oscillation in SiC JFET-based BDSs has direct impact on the stability and reliability of these circuits. Proper handling of parasitic oscillation becomes highly critical. This paper focuses on the parasitic oscillation suppression in SiC JFET-based BDSs. A parallel snubber capacitor or a series ferrite ring was often used to damp parasitic oscillation in switching circuits in the literature. However, conventionally, the snubber capacitance was obtained by time-consuming and labour-intensive trial-and-error methods. The main contribution of this study is to derive the simplified equivalent transient circuit of the SiC JFET-based BDS considering all parasitic elements and quantitatively define the reasonable range of the snubber capacitance. And the combined effect of the selected snubber capacitance and the selected ferrite ring is investigated. In the end, simulation and experimental results validate the effectiveness of the proposed method.

Effective measures for improving switching performance of SiC JFET bi‐directional switches

Silicon carbide (SiC)-based junction field-effect transistor (JFET) bi-directional switches (BDSs) have great potential in the construction of many power electronic circuits, including matrix converters, multi-level converters, solid-state breakers, and cycloconverters. However, the oscillations of BDSs during turn-on and turn-off transition have great impacts on the stability and reliability of power electronic systems. Two methods are proposed to improve the switching performance, namely using a snubber capacitor and using a ferrite ring. It is found that the use of a snubber capacitor mainly improves the turn-off transition, and the use of a ferrite ring not only damps the oscillation of current waveform during turn-on transition but also makes the waveforms cleaner and less noisy. Besides, both methods can cut down settling time significantly. The effects have been demonstrated by theoretical analysis and verified by experimental results.

Forced Current Balancing of Parallel-Connected SiC JFETs During Forward and Reverse Conduction Mode

In this paper, a thorough investigation on the parallel connection of the latest generation vertical trench silicon carbide (SiC) junction field-effect transistors (JFETs) during forward and reverse conduction is performed. Both enhancement and depletion mode SiC JFETs are examined, regarding their static and dynamic characteristics. A parametric analysis on the current sharing, reliability, and effectiveness of the parallel connection is carried out. Current asymmetry over the different JFETs is monitored via series-connected current transformers. A forced current balancing technique during forward conduction mode is achieved by controlling the time delay of the gate signal through a low-cost digital signal controller. The drain current mismatch during reverse conduction is also studied and addressed by applying similar techniques as in the forward conduction, or by adding an antiparallel power diode. The performance of paralleled JFETs is validated through simulation and experimental results at room temperature and 150 °C.

Comparative evaluation of the short-circuit withstand capability of 1.2 kV silicon carbide (SiC) power transistors in real life applications

In this paper, the response of the new generation silicon carbide (SiC) power transistors under short-circuit faults is examined. The study is focused on real life applications, where a large stray inductance is typically part of the main power loop. Three types of short-circuits are experimentally investigated and the effect of the stray inductance in each case is recorded. A comparative analysis regarding the performance of the SiC junction field effect transistors (JFETs) and SiC metal oxide field effect transistors (MOSFETs), along with the latest technology silicon (Si) MOSFETs is carried out. Maximum instantaneous power, critical energy and saturation current are the main criteria for evaluating the robustness of each power device. A destructive test is performed in order to obtain the short-circuit withstand capability and the failure mechanism of each semiconductor.

Evaluation of SiC JFET Performance During Repetitive Pulsed Switching Into an Unclamped Inductive Load

Silicon carbide (SiC) depletion mode junction field-effect transistors (JFETs) are well suited for pulsed power applications as an opening switch due to their normally ON (N-ON) nature. To assess the robustness and breakdown energy tolerance of JFETs under pulsed conditions, they must be evaluated for breakdown energy capability before failure. This is very important for circuit breaker applications due to the large voltage spikes induced during the opening of the circuit breaker while it still conducts substantial load current. These voltage spikes can drive the JFET into the breakdown voltage regime and may result in device failure if the energy dissipation is above the tolerance limit. To determine the maximum avalanche energy of the device under repetitive pulsed conditions, a N-ON SiC JFET with a nominal rating of 1200 V/13 A was driven into punchthrough breakdown using an unclamped inductive switching (UIS) circuit. The testing comprised of 4000 repetitive pulses at 25°C case temperature at a fixed gate voltage of -20 V. The drain current was increased after every 1000 pulses to increase the energy dissipated. The JFET was able to withstand 1000 pulses at a maximum energy dissipation value of 1160 mJ before failure. The JFET triode breakdown characteristics were analyzed after every 1000 pulses. The peak UIS energy of 1160 mJ corresponded to an energy density of 16.6 J/cm 2 based on their active area.

A 200 °C Safety System at Power-Up of Normally On SiC JFETs Inverters

Silicon carbide (SiC) power devices are the only commercialized components to run at high voltage and high temperature. Normally on junction field-effect transistors (JFETs) have lower on-state resistance and lower output capacitance than other SiC switches, which reduces conduction and switching losses. However, normally on power devices induce a short-circuit in voltage-fed inverters (VFI) when the gate driver is not powered prior to the bus supply. This is a power-up limitation that has not received much attention in the literature, especially for safety systems that can be used in an integrated circuit capable of running at elevated temperature. This paper describes an original solution based on SiC JFETs to secure the inverter operation at power-up without gate driver supply for the SiC JFETs. The reliability test of the protection circuit and his impact on the ageing of the JFET of the VFI are also presented. The safety system is capable of running in elevated ambient temperatures. Experimental results have been carried out in a 540 V, 10 A inverter and at ambient temperatures from 27 to 200 °C.

Comparison and Reduction of Conducted EMI in SiC JFET and Si IGBT-Based Motor Drives

This paper compares the conducted electromagnetic interference (EMI) in Si insulated gate bipolar transistor (IGBT) and silicon carbide (SiC) junction field-effect transistor (JFET) based motor drives. Two inverters, with the SiC and Si transistors, respectively, are built using the same circuit layout and investigated accordingly. Their conducted EMI levels are compared under the conditions of without filter and with traditional common mode (CM) filters. Reasons of the exhibited different noise emissions are analyzed. To verify the discussions, two inverters are tested in the CM. This allows for the identification and analysis of their maximized CM and differential mode (DM) wave shapes. It is shown that the excited parasitic oscillations during the switching transients are magnified more in the SiC JFET inverter, which is the main cause of the noise difference. Lastly, improved filtering solutions are proposed, which effectively suppressed the increased high-frequency noise due to the faster SiC switching speed.

Self-Powered Gate Driver for Normally-ON SiC JFETs: Design Considerations and System Limitations

A circuit solution to the normally-ON property of the normally-ON silicon carbide junction field-effect transistor, namely the self-powered gate driver, has been recently proposed. This letter sheds some light on the design process of the self-powered gate driver concept as well as limitations from the system perspective. It is experimentally shown that the parameters of the self-powered gate driver must be chosen taking into account a tradeoff between a fast response and stable operation of the driver. Moreover, the influence of the shoot-through current in the fast activation of the self-powered gate driver is also presented.