Silicidation Process Research Articles

Theoretical investigation of silicide Schottky barrier detector integrated in horizontal metal-insulator-silicon-insulator-metal nanoplasmonic slot waveguide

An ultracompact integrated silicide Schottky barrier detector (SBD) is designed and theoretically investigated to electrically detect the surface plasmon polariton (SPP) propagating along horizontal metal-insulator-silicon-insulator-metal nanoplasmonic slot waveguides at the telecommunication wavelength of 1550 nm. An ultrathin silicide layer inserted between the silicon core and the insulator, which can be fabricated precisely using the well-developed self-aligned silicide process, absorbs the SPP power effectively if a suitable silicide is chosen. Moreover, the Schottky barrier height in the silicide-silicon-silicide configuration can be tuned substantially by the external voltage through the Schottky effect owing to the very narrow silicon core. For a TaSi(2) detector with optimized dimensions, numerical simulation predicts responsivity of ~0.07 A/W, speed of ~60 GHz, dark current of ~66 nA at room temperature, and minimum detectable power of ~-29 dBm. The design also suggests that the device's size can be reduced and the overall performances will be further improved if a silicide with smaller permittivity is used.

NiPt salicide process improvement for 28nm CMOS with Pt(10%) additive

This study successfully demonstrates 50-80% NiSi defect reduction and P-FET 3% leakage improvement using Pt(10at.%) additive for 28nm node silicide process. Additionally, this study also discovers that lower thermal budget is required for getting same thick NiSi and better NiSi Rs distribution with higher concentration of Pt additive.

Resistance to oxidation of graphite silicided by reactive infiltration

In order to improve the oxidation resistance of graphite at high temperatures, graphite surfaces are modified by two silicidation processes involving reactive infiltration of molten silicon or, alternatively, of gaseous silicon monoxide. The resistance to oxidation of silicided graphite is studied by cyclic oxidation tests performed under a dry air flux at temperatures in the range 1550–1600 °C. During oxidation three successive regimes are evidenced: (i) initial growth of a passive silica layer on the continuous SiC superficial layer responsible for the remarkable oxidation resistance at 1550 °C; (ii) then, slow mass consumption in the intermediate composite SiC–C region; (iii) and finally, rapid local consumption of the underlying non-infiltrated porous graphite. The temporal stability of the silicided layer in air is analyzed and the reactions affecting this stability are identified. The analysis interprets the experimental findings in a satisfactory manner, especially the dramatical variation with temperature of silicided graphite lifetime observed in this temperature range.

Characteristics of Schottky barrier silicon nanocluster floating gate flash memory

The silicon nanocluster floating gate memory device based on the Schottky barrier metal-oxide-semiconductor field effect transistor (SB-MOSFET) was proposed. The silicon nanoclusters were formed via the digital gas-feeding low pressure chemical vapor deposition. Erbium silicide process was used to form the Schottky junctions at the source/drain. In addition to the SB-MOSFET operation, the program/erase times of the nonvolatile memory device were determined to be 10 ms and 100 ms under the + 18 and − 18 V gate bias conditions, respectively. Maximum memory window was 5.5 V and the charge retention characteristics were maintained with a memory window of 0.5 V at 10 6 s.

A Novel Integration of Si Schottky Diode for mmWave CMOS, Low-Power SoCs, and More

A novel manufacturable integration of Si Schottky contact/diode using the standard W-contact process (instead of the standard silicide process) is demonstrated. Up to 4× smaller junction area is enabled. Schottky barrier diode with the novel integration shows the potential to replace the bipolar junction transistor/p-n diodes for low-voltage/low-power system-on-a-chip and memory applications and for electrostatic discharge. It is also viable for complementary metal-oxide-semiconductor millimeter-wave (30-300 GHz) designs per its 1-THz cutoff frequency.

An ordered Si nanowire with NiSi2 tip arrays as excellent field emitters

A method was developed to grow ordered silicon nanowire withNiSi2 tip arrays by reacting nickel thin films on silica-coated ordered Si nanowire (NW) arrays.The coating of thin silica shell on Si NW arrays has the effect of limiting thediffusion of nickel during the silicidation process to achieve the single crystallineNiSi2 NWs.In the meantime, it relieves the distortion of the NWs caused by the strain associated with formation ofNiSi2 tomaintain the straightness of the nanowire and the ordering of the arrays. Other nickel silicide phases suchas Ni2Si and NiSi were obtained if the silicidation processes were conducted on the ordered SiNWs without a thin silica shell. Excellent field emission properties were found forNiSi2/Si NW arrays with a turnon field of 0.82 V µm − 1 and athreshold field of 1.39 V µm − 1. The field enhancement factor was calculated to be about 2440. Thestability test showed a fluctuation of about 7% with an applied field of 2.6 V µm − 1 for a period of 24 h. The excellent field emission characteristics are attributedto the well-aligned and highly ordered arrangement of the single crystallineNiSi2/Si heterostructure field emitters. In contrast to other growth methods, the present growth ofordered nickel silicide/Si NWs on silicon is compatible with silicon nanoelectronics deviceprocesses, and also provides a facile route to grow other well-aligned metal silicide NWarrays. The advantages will facilitate its applications as field emission devices.

Fabrication of SB-MOSFETs on SOI Substrate Using Ni Silicide Containing Er Interlayer

SB-MOSFETs were fabricated on SOI substrates by applying novel Schottky barrier height modulation technique of Er interlayer insertion at the interface of Ni/Si prior to Ni silicidation process. It was found that Er interlayer insertion lowered Schottky barrier height for electrons while no significant increase of the resistivity in the Er interlayer inserted films compare to pure Ni silicide films in the annealing temperature range of 500-750 oC. Effects of Er insertion to the transistor characteristics of SOI SB-MOSFETs are also discussed.

Dopant-Segregated Schottky Source/Drain FinFET With a NiSi FUSI Gate and Reduced Leakage Current

Enhanced Dopant-segregated Schottky-barrier (DSSB) FinFETs combined with a fully silicided (FUSI) gate were fabricated via single-step Ni-silicidation. Both workfunction control of the gate and a lowered effective SB-height in the source/drain junctions are simultaneously achieved by the dopant-segregated silicidation process. Moreover, the leakage current was significantly reduced with the aid of deep source/drain implantation. Therefore, it can be expected that a DSSB device with a FUSI gate have several advantages as both a logic and nonvolatile memory device. First, for a logic device, it can provide low parasitic resistance and a tunable threshold voltage. Second, for a nonvolatile memory device, the increased workfunction due to the FUSI gate can enhance the erasing characteristics by suppressing the back tunneling of electrons from the gate side as well as the programming characteristics.

Improvement of the poly-SiGe electrode contact technology for MEMS

Polycrystalline silicon–germanium (poly-SiGe) has already been shown to be an excellent structural material for microelectromechanical systems. It also enables a monolithic integration with CMOS due to its deposition temperature ⩽450 °C. An important factor in the success of this monolithic integration is the electrical resistance between MEMS and CMOS. In this paper the contact resistance between a poly-SiGe MEMS electrode and an Al-top CMOS electrode was investigated using a stacked Greek cross structure. It was significantly reduced by the use of a combined soft sputter etch and a Ti–TiN interlayer. All parameters influencing the contact resistance were identified and taken into account to determine the specific contact resistivity using a simplified model. A very low specific contact resistivity of 3.15 × 10−7 Ω cm2 was achieved on combining an Ar soft sputter etch (20 nm) and a Ti–TiN (5–20 nm) interlayer. The resistivity achieved is better than previously reported values using a complex Ni–silicide process.

Strain mapping for the semiconductor industry by dark-field electron holography and nanobeam electron diffraction with nm resolution

There is a requirement of the semiconductor industry to measure strain in semiconductor devices with nm-scale resolution. Here we show that dark-field electron holography and nanobeam electron diffraction (NBED) are both complementary techniques that can be used to determine the strain in these devices. We show two-dimensional strain maps acquired by dark holography and line profiles that have been acquired by NBED of recessed SiGe sources and drains with a variety of different gate lengths and Ge concentrations. We have also used dark-field electron holography to measure the evolution in strain during the silicidation process, showing that this can reduce the applied uniaxial compressive strain in the conduction channel by up to a factor of 3.

Enhancement of Thermal Stability in Ni Silicides on Epi-Si1 − xCx by Pt Addition

The thermal stability of nickel silicides from the Ni–Pt alloy on strained epitaxial layers was evaluated. C atoms in the epitaxial layer remain in the interface during Ni(Pt)Si formation. The decrease in interfacial energy by C segregation at the grain boundaries and interfaces enhanced the thermal stability of NiSi. The thermal stability of NiSi was greatly enhanced when Pt was added during the silicidation process. Upon increasing annealing temperatures, the sheet resistance of decreased to a lower value because a stable Ni(Pt)Si layer is formed on the epitaxial layer. The formation of a stable Ni(Pt)Si phase suppressed the agglomeration of NiSi as well as the formation of a phase.

Phase formation and texture of nickel silicides on Si 1−xC x epilayers

We investigated the phase formation and texture of nickel silicides formed during the reaction of 10 nm sputter deposited nickel with Si 1− x C x epitaxial layers on Si(1 0 0) substrates, having a carbon content between 0 and 2.5 atomic percent. It was found that both the formation temperature as well as the texture of the metal-rich phases is influenced by the amount of carbon in the Si 1− x C x layer. To determine the influence of the location of the carbon during the silicidation process we also investigated the reaction of 10 nm nickel on Si(1 0 0) substrates, where carbon was either alloyed in the nickel layer or deposited as an interlayer at the interface between the nickel and the substrate. Depending on the location of the carbon, a different thermal stability of the layer was found.

Optical metrology of Ni and NiSi thin films used in the self-aligned silicidation process

The thickness-dependent optical properties of nickel metal and nickel monosilicide (NiSi) thin films, used for self-aligned silicidation process, were characterized using spectroscopic ellipsometry. The thickness-dependent complex dielectric function of nickel metal films is shown to be correlated with the change in Drude free electron relaxation time. The change in relaxation time can be traced to the change in grain boundary (GB) reflection coefficient and grain size. A resistivity based model was used as the complementary method to the thickness-dependent optical model to trace the change in GB reflection coefficient and grain size. After silicidation, the complex dielectric function of NiSi films exhibit non-Drude behavior due to superimposition of interband absorptions arising at lower frequencies. The Optical models of the complete film stack were refined using x-ray photoelectron spectroscopy, Rutherford backscattered spectroscopy, and x-ray reflectivity (XRR).

Integrated NiSi waveguide heaters for CMOS-compatible silicon thermo-optic devices

We report the performance of NiSi-based heaters integrated with submicrometer silicon waveguides. The heaters were fabricated using a standard complementary metal-oxide-semiconductor (CMOS) silicidation process on a thin silicon slab laterally connected with a silicon rib waveguide. The intrinsic properties of such NiSi waveguide heaters were characterized by using them as thermo-optic phase shifters in a Mach-Zehnder interferometer. The power consumption P(pi) for obtaining a pi phase shift was measured to be as low as 20 mW, using CMOS-compatible drive voltages. The time constant of the thermo-optic response was less than 2.8 mus. Simulations suggest that a further reduction in the power consumption P(pi) is feasible.

Strain evolution during the silicidation of nanometer-scale SiGe semiconductor devices studied by dark field electron holography

SiGe is routinely used to induce strain in modern semiconductors in order to improve the mobility of the carriers in the channel. Due to the absence of a technique that can accurately measure the strain in these devices with nanometer-scale resolution it has been difficult to assess the effects of processing such as silicidation on the compressive strain in the conduction channel. Here we show that by using dark field electron holography, the strain evolution at various stages of the device processing can be observed, showing that the silicidation process does in fact significantly reduce the strain in the conduction channel.

Oxygen distribution in nickel silicide films analyzed by time-of-flight secondary ion mass spectrometry

The oxygen distribution in Ni 2Si and NiSi films formed during a two-step silicidation process was analyzed by time-of-flight secondary ion mass spectrometry (TOF-SIMS). TOF-SIMS mass spectra revealed that both silicon and nickel reacted with oxygen at the Ni 2Si surface. In addition, silicon nitride was formed at the surface by the reaction of silicon with nitrogen in the TiN capping layer during the first silicidation annealing. The amount of nitrogen at the NiSi surface varied with silicidation annealing temperature and with the formation conditions of the TiN capping layer. We also showed that a small amount of oxygen was penetrated into the NiSi film and strongly affected the level of junction leakage current in n +–p junctions in n-channel MOSFETs. The oxygen concentration in the NiSi film decreased with an increase in the amount of nitrogen at the NiSi surface.

Substrate-triggered GGNMOS in 65 nm CMOS process for ESD application

A novel substrate-triggered grounded-gate NMOS (GGNMOS) is verified in 65 nm CMOS silicide process. The trigger element is a PMOS controlled by the VDD bus line and no other detection circuit is needed. Compared to traditional GGNMOS, with a 50 µm trigger PMOS, the trigger voltage of the single finger structure can be reduced from 7.15 to 4.97 V and it also has lower overshoot voltage. Also the ultrathin gate oxide can be effectively protected, which is very important in nanometre circuits. For the multi-finger structure, with a 30 µm trigger PMOS the proposed structure showed a 15.9% reduction in trigger voltage and a 13.5% increment as to failure current compared to traditional GGNMOS.

Physical properties of Co-Mn-Si films on SOI preapred by silicidation process

Physical properties of Co-Mn-Si films on SOI preapred by silicidation process

Selenium Segregation for Lowering the Contact Resistance in Ultrathin-Body MOSFETs With Fully Metallized Source/Drain

We report the first integration of selenium (Se) segregation contact technology in ultrathin-body (UTB) n-MOSFET featuring Ni fully silicided source and drain. During the Ni silicidation process, the implanted Se segregated at the NiSi-n-Si interface, leading to significant reduction of Schottky barrier height and contact resistance. The UTB n-MOSFETs integrated with Se segregation (SeS) contact technology show significant external series resistance reduction and drive current performance enhancement. Drain-induced barrier lowering and gate leakage current density are not adversely affected by the SeS process.

Two-step Ni silicide process and influence of protective N2 gas

A two-step process of Ni silicide formed on bulk silicon, and the effects of different process conditions, including two-step RTA temperature and time, selective etching, and process protective nitrogen gas on the properties of the Ni silicide film have been studied. In particular, the experiments show that the quality of NiSi film is very sensitive to the process conditions of the first RTA. The experiments also show that the quality of the film is very sensitive to the flow of protective nitrogen gas. The corresponding mechanisms are discussed.