Significant Hardware Resources Research Articles

Review of Advanced Methods in Hardware Acceleration for Deep Neural Networks

Abstract: Convolutional neural networks have become very efficient in performing tasks like Object Detection providing human like accuracy. However, their practical implementation needs significant hardware resources and memory bandwidth. In recent past a lot of research is being carried out for achieving higher efficiency in implementing such neural networks in hardware. We talk about FPGAs for hardware implementation due to their flexibility for customisation for such neural network architectures. In this paper we will discuss the metrics for efficient hardware accelerator and general methods available for achieving an efficient design. Further, we will discuss the actual methods used by recent research for implementation of deep neural networks particularly for object detection related applications. These methods range from actual ASIC design like TPUs [1] for on chip acceleration, state of the art open source designs like Gemini to methods like hardware reuse, re-configurable nodes and approximation in computations as a trade-off between speed and accuracy. This paper will be a valuable summary for the researchers starting in the field of hardware accelerators design for neural networks

Optimized thread-block arrangement in a GPU implementation of a linear solver for atmospheric chemistry mechanisms

Earth system models (ESM) demand significant hardware resources and energy consumption to solve atmospheric chemistry processes. Recent studies have shown improved performance from running these models on GPU accelerators. Nonetheless, there is room for improvement in exploiting even more GPU resources.This study proposes an optimized distribution of the chemical solver's computational load on the GPU, named Block-cells. Additionally, we evaluate different configurations for distributing the computational load in an NVIDIA GPU.We use the linear solver from the Chemistry Across Multiple Phases (CAMP) framework as our test bed. An intermediate-complexity chemical mechanism under typical atmospheric conditions is used. Results demonstrate a 35× speedup compared to the single-CPU thread reference case. Even using the full resources of the node (40 physical cores) on the reference case, the Block-cells version outperforms them by 50%. The Block-cells approach shows promise in alleviating the computational burden of chemical solvers on GPU architectures.

RadarTCN: Lightweight Online Classification Network for Automotive Radar Targets Based on TCN.

Automotive radar is one of the key sensors for intelligent driving. Radar image sequences contain abundant spatial and temporal information, enabling target classification. For existing radar spatiotemporal classifiers, multi-view radar images are usually employed to enhance the information of the target and 3D convolution is employed for spatiotemporal feature extraction. These models consume significant hardware resources and are not applicable to real-time applications. In this paper, RadarTCN, a novel lightweight network, is proposed that achieves high-accuracy online target classification using single-view radar image sequences only. In RadarTCN, 2D convolution and 3D-TCN are employed to extract spatiotemporal features sequentially. To reduce data dimensionality and computational complexity, a multi-layer max pooling down-sampling method is designed in a 2D convolution module. Meanwhile, the 3D-TCN module is improved through residual pruning and causal convolution is introduced for leveraging the performance of online target classification. The experimental results demonstrate that RadarTCN can achieve high-precision online target recognition for both range-angle and range-Doppler map sequences. Compared to the reference models on the CARRADA dataset, RadarTCN exhibits better classification performance, with fewer parameters and lower computational complexity.

A semi-supervised deep learning approach for cropped image detection

Deep learning algorithms have shown great performance in multimedia forensics applications using supervised learning on large-scale labeled datasets. However, constructing such extensive labeled datasets can be challenging and costly in several multimedia forensics scenarios. Additionally, heavyweight deep learning models with complex architectures and a large number of parameters require significant hardware resources for training. To address these challenges in the context of image cropping detection, a common multimedia forensics application, we propose a semi-supervised deep learning framework capable of training on a large amount of unlabeled image samples. In this framework, we leverage a teacher model, trained on a small set of labeled image samples, to rank the confidence scores of image samples in a large-scale unlabeled dataset. By utilizing the ranked image samples, we train a student network successfully. To validate the effectiveness of our collaborative training framework across various image cropping detection scenarios, we conduct extensive experiments on a large-scale dataset. The experimental results clearly demonstrate that our semi-supervised learning approach achieved a state-of-the-art performance compared to existing supervised detection frameworks, achieving an accuracy of 91.79% on the BOSSbase dataset and 89.23% on the Alaska dataset. Furthermore, we conducted in-depth research on various factors that influence detection performance in the context of semi-supervised learning. These factors include pairings of teacher–student models, the top-K selection approach, the number of unlabeled samples, the number of iterations in self-training, and the proportion of high-confidence samples using in semi-supervised learning.

Backpropagation-Free Deep Learning with Recursive Local Representation Alignment

Training deep neural networks on large-scale datasets requires significant hardware resources whose costs (even on cloud platforms) put them out of reach of smaller organizations, groups, and individuals. Backpropagation (backprop), the workhorse for training these networks, is an inherently sequential process that is difficult to parallelize. Furthermore, researchers must continually develop various specialized techniques, such as particular weight initializations and enhanced activation functions, to ensure stable parameter optimization. Our goal is to seek an effective, neuro-biologically plausible alternative to backprop that can be used to train deep networks. In this paper, we propose a backprop-free procedure, recursive local representation alignment, for training large-scale architectures. Experiments with residual networks on CIFAR-10 and the large benchmark, ImageNet, show that our algorithm generalizes as well as backprop while converging sooner due to weight updates that are parallelizable and computationally less demanding. This is empirical evidence that a backprop-free algorithm can scale up to larger datasets.

An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks

Practical implementation of deep neural networks (DNNs) demands significant hardware resources, necessitating high computational power and memory bandwidth. While existing field-programmable gate array (FPGA)–based DNN accelerators are primarily optimized for fast single-task performance, cost, energy efficiency, and overall throughput are crucial considerations for their practical use in various applications. This article proposes a performance-centric pipeline Coordinate Rotation Digital Computer (CORDIC)–based MAC unit and implements a scalable CORDIC-based DNN architecture that is area- and power-efficient and has high throughput. The CORDIC-based neuron engine uses bit-rounding to maintain input-output precision and minimal hardware resource overhead. The results demonstrate the versatility of the proposed pipelined MAC, which operates at 460 MHz and allows for higher network throughput. A software-based implementation platform evaluates the proposed MAC operation’s accuracy for more extensive neural networks and complex datasets. The DNN accelerator with parameterized and modular layer-multiplexed architecture is designed. Empirical evaluation through Pareto analysis is used to improve the efficiency of DNN implementations by fixing the arithmetic precision and optimal pipeline stages. The proposed architecture utilizes layer-multiplexing, a technique that effectively reuses a single DNN layer to enhance efficiency while maintaining modularity and adaptability for integrating various network configurations. The proposed CORDIC MAC-based DNN architecture is scalable for any bit-precision network size, and the DNN accelerator is prototyped using the Xilinx Virtex-7 VC707 FPGA board, operating at 66 MHz. The proposed design does not use any Xilinx macros, making it easily adaptable for ASIC implementation. Compared with state-of-the-art designs, the proposed design reduces resource use by 45% and power consumption by 4× without sacrificing performance. The accelerator is validated using the MNIST dataset, achieving 95.06% accuracy, only 0.35% less than other cutting-edge implementations.

Direct Interface Circuit for Capacitive Sensors Affected by Parasitic Series Resistances

This article presents a novel circuit to directly interface a capacitive sensor affected by parasitic series resistances to a digital processor (DP). The presence of such resistances distorts the estimation of the capacitance to be measured. Current measurement procedures for these sensors, such as impedance-frequency characteristics, are complex and require significant hardware resources, power consumption, and time. To eliminate these drawbacks, a new circuit based on the so-called direct interface circuits (DICs) is introduced, which performs the digital reading of the sensors taking advantage of the presence of DPs in many applications. The hardware requirements in the new design are minimal: just two resistors and an operational amplifier in addition to the DP. The circuit requires only two time measurements to estimate sensor capacitance. These are obtained during a single capacitor charging-discharging process, simultaneously reducing power consumption and measurement time. The circuit has been implemented using a field-programmable gate array (FPGA), as the DP, in a general-purpose board to evaluate its performance. Although it is not an application-specific design, the circuit shows a maximum systematic error of 0.37% for capacitances in the 100 pF–96 nF range with parasitic series resistances up to 1200 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> . The maximum measurement time for this range is just 4.5 ms.

Efficiency of integration between sensor networks and clouds

Numerous wireless sensor networks (WSN) applications include monitoring and controlling various conditions in the environment, industry, healthcare, medicine, military affairs, agriculture, etc. The life of sensor nodes largely depends on the power supply type, communication ability, energy storage capacity and energy management mechanisms. The collection and transmission of sensor data streams from sensor nodes lead to the depletion of their energy. At the same time, the storage and processing of this data require significant hardware resources. Integration between clouds and sensor networks is an ideal solution to the limited computing power of sensor networks, data storage and processing. One of the main challenges facing systems engineers is to choose the appropriate protocol for integrating sensor data into the cloud structure, taking into account specific system requirements. This paper presents an experimental study on the effectiveness of integration between sensor networks and the cloud, implemented through three protocols HTTP, MQTT and MQTT-SN. A model for studying the integration of sensor network - Cloud with the communication models for integration - request-response and publish- subscribe, implemented with HTTP, MQTT and MQTT-SN. The influence of the number of transmitted data packets from physical sensors to the cloud on the transmitted data delay to the cloud, the CPU and memory load was studied. After evaluating the results of sensor network and cloud integration experiments, the MQTT protocol is the most efficient in terms of data rate and power consumption.

Aggregated Boolean Query Processing for Document Retrieval in Edge Computing

Search engines use significant hardware and energy resources to process billions of user queries per day, where Boolean query processing for document retrieval is an essential ingredient. Considering the huge number of users and large scale of the network, traditional query processing mechanisms may not be applicable since they mostly depend on a centralized retrieval method. To remedy this issue, this paper proposes a processing technique for aggregated Boolean queries in the context of edge computing, where each sub-region of the network corresponds to an edge network regulated by an edge server, and the Boolean queries are evaluated in a distributed fashion on the edge servers. This decentralized query processing technique has demonstrated its efficiency and applicability for the document retrieval problem. Experimental results on two real-world datasets show that this technique achieves high query performance and outperforms the traditional centralized methods by 2–3 times.

The Ocean Gene Atlas v2.0: online exploration of the biogeography and phylogeny of plankton genes.

Testing hypothesis about the biogeography of genes using large data resources such as Tara Oceans marine metagenomes and metatranscriptomes requires significant hardware resources and programming skills. The new release of the ‘Ocean Gene Atlas’ (OGA2) is a freely available intuitive online service to mine large and complex marine environmental genomic databases. OGA2 datasets available have been extended and now include, from the Tara Oceans portfolio: (i) eukaryotic Metagenome-Assembled-Genomes (MAGs) and Single-cell Assembled Genomes (SAGs) (10.2E+6 coding genes), (ii) version 2 of Ocean Microbial Reference Gene Catalogue (46.8E+6 non-redundant genes), (iii) 924 MetaGenomic Transcriptomes (7E+6 unigenes), (iv) 530 MAGs from an Arctic MAG catalogue (1E+6 genes) and (v) 1888 Bacterial and Archaeal Genomes (4.5E+6 genes), and an additional dataset from the Malaspina 2010 global circumnavigation: (vi) 317 Malaspina Deep Metagenome Assembled Genomes (0.9E+6 genes). Novel analyses enabled by OGA2 include phylogenetic tree inference to visualize user queries within their context of sequence homologues from both the marine environmental dataset and the RefSeq database. An Application Programming Interface (API) now allows users to query OGA2 using command-line tools, hence providing local workflow integration. Finally, gene abundance can be interactively filtered directly on map displays using any of the available environmental variables. Ocean Gene Atlas v2.0 is freely-available at: https://tara-oceans.mio.osupytheas.fr/ocean-gene-atlas/.

A stochastic computing architecture for local contrast and mean image thresholding algorithm

AbstractImage binarization algorithms in document image analysis divide pixel values into two groups, including white as background and black as foreground. Among others, the local contrast and mean (LCM)‐based thresholding algorithm offers excellent performance in processing degraded documents. This algorithm, however, is susceptible to noise and requires significant hardware resources. In this paper, an energy‐efficient and fault‐tolerant architecture is proposed for implementing the LCM algorithm in stochastic computing (SC). Leveraging correlated input bitstreams, this architecture saves energy and improves the fault tolerance of the implementation. Experimental results show that the proposed LCM stochastic architecture significantly outperforms the stochastic implementation of the Sauvola algorithm in terms of both binarization accuracy and hardware overhead and energy consumption. Even using 16‐bit streams, the proposed circuit produces an error rate lower than 5%. The stochastic implementation of the LCM algorithm using a 16‐bit length FSM‐based LD sequence is 22 times less in area, 26 times less in total power, 28 times less in energy consumption and more fault‐tolerant than the conventional 8‐bit bit‐width weighted binary with the same frequency constraints.

КРИПТОГРАФИЧЕСКАЯ КОНТЕЙНЕРИЗАЦИЯ ДАННЫХ В ОБРАБОТКЕ НЕЙРОННЫХ СЕТЕЙ ГЛУБОКОГО ОБУЧЕНИЯ

Introduction: the existing development of methods for ensuring information security in the field of information technology allows you to control the confidentiality of personal data at variable levels. Hardware solutions can be portable cryptographic keys, as well as narrowly targeted biometric identification devices. Software solutions are methods of static verification using sequences and side-tools for deploying data virtualization systems. The main problem that stands out among the methods described above is the need for additional hardware that acts as tokens, infrared cameras, and biometric identification sensors. An alternative problem is the lack of security of software solutions, since the presence of zero-day vulnerabilities can reduce security, which leads to the possibility of interception of confidential data by third parties. Purpose of the research is expressed in the analysis and development of software methods and algorithms for ensuring data security based on containerization methods. The developed software solution allows you to perform application tasks in a secure container, while the implemented authentication methods support the ability to identify an individual both using sequences and using the Windows Hello application programming interface. Methods used: security methods and algorithms aimed at implementing a unique cryptographic algorithm. The results of the studied methods and algorithms for scanning a bounded shell allow us to variatively select the optimal outcomes of internal process instances along with the implementation of cryptographic methods. Application software is based on the joint use of virtualization tools and methods of interaction through neural network technologies. The isolation of this solution from alternative methods lies in the possibility of using the container without significant hardware resources and lack of primary knowledge in configuring the software module. Practical significance lies in the possibility of using methods and algorithms in the construction of secure jobs in small and medium-sized businesses.

Classification of Copper Minerals by Handheld Laser-Induced Breakdown Spectroscopy and Nonnegative Tensor Factorisation.

Laser-induced breakdown spectroscopy (LIBS) analysers are becoming increasingly common for material classification purposes. However, to achieve good classification accuracy, mostly noncompact units are used based on their stability and reproducibility. In addition, computational algorithms that require significant hardware resources are commonly applied. For performing measurement campaigns in hard-to-access environments, such as mining sites, there is a need for compact, portable, or even handheld devices capable of reaching high measurement accuracy. The optics and hardware of small (i.e., handheld) devices are limited by space and power consumption and require a compromise of the achievable spectral quality. As long as the size of such a device is a major constraint, the software is the primary field for improvement. In this study, we propose a novel combination of handheld LIBS with non-negative tensor factorisation to investigate its classification capabilities of copper minerals. The proposed approach is based on the extraction of source spectra for each mineral (with the use of tensor methods) and their labelling based on the percentage contribution within the dataset. These latent spectra are then used in a regression model for validation purposes. The application of such an approach leads to an increase in the classification score by approximately 5% compared to that obtained using commonly used classifiers such as support vector machines, linear discriminant analysis, and the k-nearest neighbours algorithm.

High throughput unified architecture of LEA algorithm for image encryption

Among instances when the data and image security in resource constrained environment (smart devices and the like) are to be taken into consideration, lightweight encryption algorithms accede in popularity and are deemed of to be of great merit. In devices as those of the sort mentioned, reducing both power consumption and gate count is always a prime concern. LEA, therefore, triumphs on merit, owing to its low consumption levels of hardware resources, which itself is a result of the adaption of simple modular addition, bitwise rotation and bitwise XOR (ARX) operation instead of the relatively more complex S-box technique. The algorithm in question supports keys of varying sizes three, to be precise: 128, 192 and 256-bit for the intent of providing three levels of image and data security. The hardware implementation of the LEA algorithm for the varying key sizes as mentioned above share significant kinship and hardware resources. This paper puts forward the proposition regarding a high speed low area unified architecture for LEA algorithm for three different sizes of key. The individual hardware implementations of the three key sizes tend to consume more hardware resources than those involved in the proposed unified architecture. The pipelined implementation of the proposed design improves operating frequency to a significant degree, with a little increase in the hardware costs. The design proposed in this paper notably supports three varying tile sizes, i.e. 256×256,128×128,64×64, of an input image. As resolution of an input image may not necessarily be an integer multiple of the size of tile, smaller tile sizes at the image boundary can also be handled by the same architecture. The design hereby proposed has been implemented on both UMC ASIC 0.09-μm and XC5VLX330T FPGA platforms and achieved maximum operating frequencies of 740 MHz and 292 MHz respectively. As its increasingly evident on account of the FPGA implementation outcomes, the proposed unified architecture results in vastly improved levels of operating frequency (34%, 33% and 131%) as opposed to the individually available LEA architectures (corresponding to three different key sizes: 128, 192 and 256-bit, respectively). Proposed architecture shows 28%, 35% and 45% increment in the hardware resources with respect to available LEA architectures with single key. The incorporation of the unified key generation technique and pipeline implementation of the algorithm are the main reasons for the more hardware utilization.

A Pareto-Optimal Multi-filter Architecture on FPGA for Image Processing Applications

Conventional two-dimensional filters for digital image processing are computationally intensive and consume significant hardware resources on field-programmable gate array (FPGA). Multiple filters implemented at a very low area and power budget are essential requirements of modern embedded systems for performing diversified image processing tasks. The previously reported multi-filter architectures are infeasible, since they do not provide pareto-optimal solution in terms of flexibility, hardware cost and versatility. This work presents a pareto-optimal multi-filter architecture that cater to these three major design concerns. The high degree of flexibility is induced in design by the deployment of an efficient customized 2,3 tree structure. This implements successive odd filter kernels in 44 different combinations with the maximum \(9 \times 9\) size, without hardware blocking. These implemented filters are structurally optimized and versatile for realizing diverse filter types at a very low cost. The complete design occupies only 2319 Slices on Xilinx Artix-7 FPGA and performs at 111 fps for full HD resolution with a very low power consumption of 197.5 mW. With these attributes, the proposed multi-filter architecture implements multiple filters of diverse types at very low area and power; this makes it well suited for image processing applications in real time. Finally, the proposed architecture is validated using Digilent Nexys4 development board.

DC-Link Voltage Balance Control Strategy Based on Multidimensional Modulation Technique for Quasi-Z-Source Cascaded Multilevel Inverter Photovoltaic Power System

A dc-link voltage balancing control strategy for quasi-Z-source cascaded H-bridge (qZS-CHB) inverter photovoltaic (PV) power system is proposed by using multidimensional pulse-width modulation (MD-PWM) technique. The qZS-CHB PV system usually employs proportional-integral (PI) regulators based closed-loop control methods to balance dc-link voltages, combining with distributed maximum power point tracking and grid-tie power control. These require significant control computations and hardware resources for multiple modules based qZS-CHB system. The proposed MD-PWM for the qZS-CHB inverter performs shoot-through behavior based on geometric representation of the output voltage ranges of each H-bridge in coordinate axes. All possible switching sequences of the qZS-CHB inverter are taken into account to choose the most suitable sequence that can balance dc-link voltages of qZS modules in the qZS-CHB PV power system. When compared with the state-of-the-art of voltage balancing control methods, the proposed control strategy has advantages: 1) The computation is low because there is no PI controller, while the stability of the whole system is improved; and 2) there is a reliable balancing capability with fast regulation of dc-link voltages, owing to no extra controller parameters and handling the voltage balance in each control cycle. Simulation and experimental results of qZS-CHB inverter based grid-tie PV power system verify the proposed dc-link voltage balancing control technique.

Dynamic contrast-enhanced photoacoustic imaging using photothermal stimuli-responsive composite nanomodulators

Molecular photoacoustic imaging has shown great potential in medical applications; its sensitivity is normally in pico-to-micro-molar range, dependent on exogenous imaging agents. However, tissue can produce strong background signals, which mask the signals from the imaging agents, resulting in orders of magnitude sensitivity reduction. As such, an elaborate spectral scan is often required to spectrally un-mix the unwanted background signals. Here we show a new single-wavelength photoacoustic dynamic contrast-enhanced imaging technique by employing a stimuli-responsive contrast agent. Our technique can eliminate intrinsic background noises without significant hardware or computational resources. We show that this new contrast agent can generate up to 30 times stronger photoacoustic signals than the concentration-matched inorganic nanoparticle counterparts. By dynamically modulating signals from the contrast agents with an external near-infrared optical stimulus, we can further suppress the background signals leading to an additional increase of more than five-fold in imaging contrast in vivo.

EFFICIENT CFD/CSD COUPLING METHODS FOR AEROELASTIC APPLICATIONS

A fast aeroelastic numerical simulation method using CFD/CSD coupling are developed. Generally, aeroelastic numerical simulation costs much time and significant hardware resources with CFD/CSD coupling. In this paper, dynamic grid method, full implicit scheme, parallel technology and improved coupling method are researched for efficiency simulation. An improved Delaunay graph mapping method is proposed for efficient dynamic grid deform. Hybrid grid finite volume method is used to solve unsteady flow fields. The dual time stepping method based on parallel implicit scheme is used in temporal discretization for efficiency simulation. An approximate system of linear equations is solved by the GMRES algorithm with a LU-SGS preconditioner. This method leads to a significant increase in performance over the explicit and LU-SGS implicit methods. A modification of LU-SGS is proposed to improve the parallel performance. Parallel computing overs a very effective way to improve our productivity in doing CFD/CFD coupling analysis. Improved loose coupling method is an efficiency way over the loose coupling method and tight coupling method. 3D wing's aeroelastic phenomenon is simulated by solving Reynolds-averaged Navier–Stokes equations using improved loose coupling method. The flutter boundary is calculated and agrees well with experimental data. The transonic hole is very clear in numerical simulation results.

A Committee Machine Gas Identification System Based on Dynamically Reconfigurable FPGA

This paper proposes a gas identification system based on the committee machine (CM) classifier, which combines various gas identification algorithms, to obtain a unified decision with improved accuracy. The CM combines five different classifiers: K nearest neighbors (KNNs), multilayer perceptron (MLP), radial basis function (RBF), Gaussian mixture model (GMM), and probabilistic principal component analysis (PPCA). Experiments on real sensors' data proved the effectiveness of our system with an improved accuracy over individual classifiers. Due to the computationally intensive nature of CM, its implementation requires significant hardware resources. In order to overcome this problem, we propose a novel time multiplexing hardware implementation using a dynamically reconfigurable field programmable gate array (FPGA) platform. The processing is divided into three stages: sampling and preprocessing, pattern recognition, and decision stage. Dynamically reconfigurable FPGA technique is used to implement the system in a sequential manner, thus using limited hardware resources of the FPGA chip. The system is successfully tested for combustible gas identification application using our in-house tin-oxide gas sensors.

A Comparison of TMR With Alternative Fault-Tolerant Design Techniques for FPGAs

With growing interest in the use of SRAM-based FPGAs in space and other radiation environments, there is a greater need for efficient and effective fault-tolerant design techniques specific to FPGAs. Triple-modular redundancy (TMR) is a common fault mitigation technique for FPGAs and has been successfully demonstrated by several organizations. This technique, however, requires significant hardware resources. This paper evaluates three additional mitigation techniques and compares them to TMR. These include quadded logic, state machine encoding, and temporal redundancy, all well-known techniques in custom circuit technologies. Each of these techniques are compared to TMR in both area cost and fault tolerance. The results from this paper suggest that none of these techniques provides greater reliability and often require more resources than TMR.