Direct Interface Circuit for Capacitive Sensors Affected by Parasitic Series Resistances

Abstract

This article presents a novel circuit to directly interface a capacitive sensor affected by parasitic series resistances to a digital processor (DP). The presence of such resistances distorts the estimation of the capacitance to be measured. Current measurement procedures for these sensors, such as impedance-frequency characteristics, are complex and require significant hardware resources, power consumption, and time. To eliminate these drawbacks, a new circuit based on the so-called direct interface circuits (DICs) is introduced, which performs the digital reading of the sensors taking advantage of the presence of DPs in many applications. The hardware requirements in the new design are minimal: just two resistors and an operational amplifier in addition to the DP. The circuit requires only two time measurements to estimate sensor capacitance. These are obtained during a single capacitor charging-discharging process, simultaneously reducing power consumption and measurement time. The circuit has been implemented using a field-programmable gate array (FPGA), as the DP, in a general-purpose board to evaluate its performance. Although it is not an application-specific design, the circuit shows a maximum systematic error of 0.37% for capacitances in the 100 pF–96 nF range with parasitic series resistances up to 1200 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> . The maximum measurement time for this range is just 4.5 ms.