A Pareto-Optimal Multi-filter Architecture on FPGA for Image Processing Applications

Abstract

Conventional two-dimensional filters for digital image processing are computationally intensive and consume significant hardware resources on field-programmable gate array (FPGA). Multiple filters implemented at a very low area and power budget are essential requirements of modern embedded systems for performing diversified image processing tasks. The previously reported multi-filter architectures are infeasible, since they do not provide pareto-optimal solution in terms of flexibility, hardware cost and versatility. This work presents a pareto-optimal multi-filter architecture that cater to these three major design concerns. The high degree of flexibility is induced in design by the deployment of an efficient customized 2,3 tree structure. This implements successive odd filter kernels in 44 different combinations with the maximum \(9 \times 9\) size, without hardware blocking. These implemented filters are structurally optimized and versatile for realizing diverse filter types at a very low cost. The complete design occupies only 2319 Slices on Xilinx Artix-7 FPGA and performs at 111 fps for full HD resolution with a very low power consumption of 197.5 mW. With these attributes, the proposed multi-filter architecture implements multiple filters of diverse types at very low area and power; this makes it well suited for image processing applications in real time. Finally, the proposed architecture is validated using Digilent Nexys4 development board.