Signed-digit Number Representation Research Articles

Difference Adder Graph Algorithm for Reducing LUT Size

The current study introduces an implementation of the Difference Adder Graph Algorithm (DAGA) using Verilog. DAGA, rooted in graph theory and adder circuits, aims to diminish Look Up Tables (LUTs) and power consumption in Field Programmable Gate Arrays (FPGAs). By reducing the number of LUTs required for a specific functionality, DAGA offers a promising alternative for digital circuit optimization. To evaluate its efficacy, the paper contrasts DAGA with the Multiple Constant Multiplication (MCM) method, which leverages Carry Save Adder (CSA) architecture and exploits signed-digit number representations to minimize LUT usage. Experimental findings reveal DAGA's superiority over MCM in both area and power utilization reduction. Implementation details and results indicate a remarkable 49.29% reduction in LUT count and a corresponding 41.8% decrease in power consumption for digital circuits. These outcomes underscore the effectiveness of DAGA in enhancing FPGA efficiency, highlighting its potential as a valuable tool for digital circuit designers seeking to optimize performance and power utilization.

Design and Implementation of Fast Booth-2 Multiplier on Artix FPGA

Abstract Now a day’s speed is very important to meet the requirement of user in today’s chips. We want faster smart phones, laptops and other gadgets that can work at a speed even beyond our imagination. In this paper we have designed a fast multiplier which can provide better results. RBSD stands for Redundant Binary Signed Digit number system which enables fast computing by reducing carry propagation time as carry is not propagated to later stages. This number system is signed digit number representation. This RBSD multiplier is implemented using VIVADO 2019.2 version. The multiplier is implemented in VHDL language. Although there is a slight increase in the delay using VIVADO Multiplier, there is a significant decrease in the number of LUT used. We have used artix FPGA[4] with part number xc7a200tisbv484.

Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

Efficient signed-digit-to-canonical-signed-digit recoding circuits

In this study, we propose a new signed-digit-to-canonical-signed-digit recoding circuit based on parallel prefix structures. Several articles have been devoted to the study of canonical signed-digit recoding circuits. However, most of those re-code from 2's complement binary number representation. Unlike those, our proposed architectures convert from signed-digit number representation. The circuit structure is somewhat different from those in previous articles, because each digit in the input is accompanied by its sign. We evaluate the proposed circuit and compare it with a circuit based on the conditional sum structure. We show that the proposed architectures performs faster by 30% or more than the circuit based on the conditional sum structure.

All-optical polarization-encoded negabinary signed-digit adder designs using terahertz-optical-asymmetric-demultiplexer switches

Incontrast to intensity-encoded negabinary modified signed-digit number representation, a polarization-encoding scheme is proposed to design all-optical adders. The utilization of the proposed polarization-encoding produces more efficient circuits in terms of gates numbers and circuit delays. Three all-optical adder circuits are designed using Terahertz-Optical-Asymmetric-Demultiplexer (TOAD) switches,polarization beam splitters, polarization converters, and beam combiners. Itwill be shown that the proposed circuits utilize 51.7%, 45.5%, and 21% less gates and they are faster by 44.4%, 42.9%, and 40%, respectively, than thecorresponding intensity-encoded circuits.

Ultra-fast all-optical polarization-encoded modified signed-digit addition using terahertz-optical-asymmetric-demultiplexer (TOAD) switches

In this paper, enhanced designs for ultra-fast all-optical circuits based on the terahertz-optical-asymmetric-demultiplexer (TOAD) adders are proposed. The high speed is achieved due to the use of the nonlinear optical materials and the nonbinary modified signed-digit (MSD) number representation. The proposed all-optical circuits use polarized light to present the trinary digits of the MSD numbers. It will be shown that the polarization-encoded MSD adder uses much less TOADs switches (37.5% less) and it is faster by 33.33% compared to the intensity-encoded ones.

All-optical negabinary adders using Mach–Zehnder interferometer

In contrast to optoelectronics, all-optical adders are proposed where all-optical signals are used to represent the input numbers and the control signals. In addition, the all-optical adders use the negabinary modified signed-digit number representation (an extension of the negabinary number system) to represent the input digits. Further, the ultra-speed of the designed circuits is achieved due to the use of ultra-fast all-optical switching property of the semiconductor optical amplifier and Mach–Zehnder interferometer (SOA–MZI). Furthermore, two-bit per digit binary encoding scheme is employed to represent the trinary values of the negabinary modified signed-digits.

On “A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters”

A thorough analysis of the paper above revealed several controversial arguments about the superiority of binary representation over canonical signed digits (CSD) for common subexpression elimination (CSE). It was improper to model the number of logic operators (LO) required after CSE as a linear sum of independently weighted numbers of nonzero bits, common subexpressions and unpaired bits. The logic depth (LD) penalty of binary CSE had been deemphasized by the errors in the reported LD. This comment corrects the LD of contention resolution algorithm, and points out some contradictions with reference to the latest experimentation of binary, CSD and minimal signed digit number representations for CSE. Upon correcting the error in the reported filter lengths for different stopband attenuations of digital advanced mobile phone system specification, the LO and LD data of the CSE algorithms compared in the above paper are recalculated using the corrected filter coefficient sets.

Improved all-optical modified signed-digit adders using semiconductor optical amplifier and Mach–Zehnder interferometer

In this paper, we present improved all-optical circuits that implement ultra-fast adders based on the carry-free property of the modified signed-digit (MSD) number representation. The all-optical realizations are based on semiconductor optical amplifier (SOA) and Mach–Zehnder interferometer (MZI) switches, which represent one of the most promising solutions due to their compact size, thermal stability and low power operation. Several all-optical circuit designs are proposed with the objective to minimize the number of the SOA–MZI switches, the time delay in the adders and some other optical elements. The proposed circuits are more efficient comparing to previously published ones in terms of the number of optical components (less by 50%) as well as the operational speed (faster by 50%).

Circuit designs of ultra-fast all-optical modified signed-digit adders using semiconductor optical amplifier and Mach–Zehnder interferometer

The need for increasingly high-speed digital optical systems and optical processors demands ultra-fast all-optical logic and arithmetic units. In this paper, we combine the attractive and powerful parallelism property of the modified signed-digit (MSD) number representation with the ultra-fast all-optical switching property of the semiconductor optical amplifier and Mach–Zehnder interferometer (SOA–MZI) to design and implement all-optical MSD adder/subtracter circuits. Non-minimized and minimized techniques are presented to design and realize efficient circuits to perform arithmetic operations. Several all-optical circuits’ designs are proposed with the objective to minimize the number of the SOA–MZI switches, the time delay units in the adders, and other optical elements. To use the switching property of the SOA–MZI structure, two bits per digit binary encoding for each of the trinary MSD digits are used. The proposed optical circuits will be very helpful in developing hardware modules for optical digital computing processors.

An efficient signed digit montgomery multiplication for RSA

In this paper we present an efficient Montgomery multiplier using the signed digit number representation suitable for modular exponentiation, which is the main operation of RSA. The multiplier consists of one level of signed digit adder plus multiplexer through a precomputation. We design the multiplier with the improved signed digit adder using SAMSUNG STD [email protected] 1.8V CMOS Standard Cell Library and compare to multipliers with other previous adders. The proposed modular multiplier can be applied to public key cryptosystems based on integer arithmetic such as RSA, DSA or ECC.

Forward and Reverse Converters and Moduli Set Selection in Signed-Digit Residue Number Systems

This paper presents an investigation into using a combination of two alternative digital number representations; the residue number system (RNS) and the signed-digit (SD) number representation in digital arithmetic circuits. The combined number system is called RNS/SD for short. Since the performance of RNS/SD arithmetic circuits depends on the choice of the moduli set (a set of pairwise prime numbers), the purpose of this work is to compare RNS/SD number systems based on different sets. Five specific moduli sets of different lengths are selected. Moduli-set-specific forward and reverse RNS/SD converters are introduced for each of these sets. A generic conversion technique for moduli sets consisting of any number of elements is also presented. Finite impulse response (FIR) filters are used as reference designs in order to evaluate the performance of RNS/SD processing. The designs are evaluated with respect to delay and circuit area in a commercial 0.13 μm CMOS process. For the case of FIR filters it is shown that generic moduli sets with five or six moduli results in designs with the best area × delay products.

A unified architecture for a public key cryptographic coprocessor

This paper presents a unified architecture for public key cryptosystems that can support the operations of the Rivest–Shamir–Adleman cryptogram (RSA) and the elliptic curve cryptogram (ECC). A hardware solution is proposed for operations over finite fields GF ( p ) and GF ( 2 p ) . The proposed architecture presents a unified arithmetic unit which provides the functions of dual-field modular multiplication, dual-field modular addition/subtraction, and dual-field modular inversion. A new adder based on the signed-digit (SD) number representation is provided for carry-propagated and carry-less operations. The critical path of the proposed design is reduced compared with previous full adder implementation methods. Experimental results show that the proposed design can achieve a clock speed of 1 GHz using 776 K gates in a 0.09 μm CMOS standard cell technology, or 150 MHz using 5227 CLBs in a Xilinx Virtex 4 FPGA. While the different technologies, platforms and standards make a definitive comparison difficult, based on the performance of our proposed design, we achieve a performance improvement of between 30% and 250% when compared with existing designs.

Performance Evaluation of Signed-Digit Architecture for Weighted-to-Residue and Residue-to-Weighted Number Converters with Moduli Set (2n-1, 2n, 2n+1)

High-speed signed-digit (SD) architectures for weighted-to-residue (WTOR) and residue-to-weighted (RTOW) number conversions with the moduli set (2n, 2n-1, 2n+1) are proposed. The complexity of the conversion has been greatly reduced by using compact forms for the multiplicative inverse and the properties of modular arithmetic. The simple relationships of WTOR and RTOW number conversions result in simpler hardware requirements for the converters. The primary advantages of our method are that our conversions use the modulo m signed-digit adder (MSDA) only and that the constructions are simple. We also investigate the modular arithmetic between binary and SD number representation using circuit designs and a simulation, and the results show the importance of SD architectures for WTOR and RTOW number conversions. Compared to other converters, our methods are fast and the execution times are independent of the word length. We also propose a high-speed method for converting an SD number to a binary number representation.

Signed digit addition and related operations with threshold logic

Assuming signed digit number representations, we investigate the implementation of some addition related operations assuming linear threshold networks. We measure the depth and size of the networks in terms of linear threshold gates. We show first that a depth-2 network with O(n) size, weight, and fan-in complexities can perform signed digit symmetric functions. Consequently, assuming radix-2 signed digit representation, we show that the two operand addition can be performed by a threshold network of depth-2 having O(n) size complexity and O(1) weight and fan-in complexities. Furthermore, we show that, assuming radix-(2n-1) signed digit representations, the multioperand addition can be computed by a depth-2 network with O(n/sup 3/) size with the weight and fan-in complexities being polynomially bounded. Finally, we show that multiplication can be performed by a linear threshold network of depth-3 with the size of O(n/sup 3/) requiring O(n/sup 3/) weights and O(n/sup 2/ log n) fan-in.

Signed-digit arithmetic for optical computing: digit grouping and pixel assignment for spatial encoding

Novel fully parallel one-step adders that use the redundant signed-digit number representation are proposed for optical computing. A new method for spatially encoding the signed-digit is proposed based on digit grouping and pixel assignment. The scheme of digital grouping of the signed-digit numbers enables a huge reduction of the number of symbolic substitution computation rules involved in the arithmetic computations and consequently increases the speed of arithmetic operations. Furthermore, the proposed spatial encoding scheme effectively increases the space bandwidth product of the spatial light modulators and decreases the size of the matched spatial filters of the optical system.

5-digit overlapped-scanning technique for the modified radix-4 recoding of signed-binary numbers

The well known modified Booth recoding technique uses 3-bit overlapped-scanning of two's complement (TC) multipliers for the area-time efficient multiplication of TC numbers. The authors present a novel recoding technique which employs 5-digit overlapped-scanning of signed-binary (SB) multipliers to achieve area–time efficient multiplication of SB numbers. The proposed recoding technique converts SB multipliers into their corresponding modified radix-4 signed-digit (SD) number representation in parallel, leading to two important practical advantages. First, it reduces the number of intermediate partial products formed during the multiplication process by a factor of two. Secondly, it eliminates an otherwise extra addition associated with the formation of each partial product. This elimination is made possible by restricting the recoded multiplier digits to 0, ±1, or ±2, only, effectively eliminating the need for multiplication by ±3. These two features lead to high-speed area-efficient SB multiplication suitable for modern high-performance VLSI and ASIC implementations.

Two-step optoelectronic quaternary signed-digit adder using optical correlation

A symbolic substitution (SS) based optical numeric processor using quaternary signed-digit (QSD) number representations is proposed. Also, we propose new joint spatial encodings for the QSD numbers that reduce the SS computation rules involved in the processor. Optoelectronic implementation of the proposed QSD adder is feasible. The proposed adder is more compact than recently reported QSD counterparts.

Recoding algorithms for the modified signed-digit numbers for parallel digital computing

The modified signed-digit number representation is a redundant number system with radix=2. This number system allows limited carry and borrow propagation for addition and subtraction operations. In this paper, symmetrical and non-symmetrical special parallel recoding algorithms for the modified signed-digit numbers are proposed for carry-free arithmetic. Multi-bit parallel digital circuits are presented using AND-OR and/or OR-AND realizations. Also, transformation techniques between the proposed recoding algorithms are provided.

Optoelectronic recoded and nonrecoded trinary signed-digit adder that uses optical correlation

A symbolic-substitution-based optical numeric processor that uses recoded and nonrecoded trinary signed-digit (TSD) number representations is proposed. Also, we propose new joint spatial encodings for the TSD numbers that reduce the symbolic-substitution computation rules involved in the processor. Optoelectronic implementation of the proposed recoded adder is feasible. Also, the nonrecoded TSD addition can be performed optically in two steps. Both the proposed recoded and nonrecoded adders are more compact than a recently reported modified signed-digit counterpart and use fewer correlators and spatial light modulators.