Abstract

The well known modified Booth recoding technique uses 3-bit overlapped-scanning of two's complement (TC) multipliers for the area-time efficient multiplication of TC numbers. The authors present a novel recoding technique which employs 5-digit overlapped-scanning of signed-binary (SB) multipliers to achieve area–time efficient multiplication of SB numbers. The proposed recoding technique converts SB multipliers into their corresponding modified radix-4 signed-digit (SD) number representation in parallel, leading to two important practical advantages. First, it reduces the number of intermediate partial products formed during the multiplication process by a factor of two. Secondly, it eliminates an otherwise extra addition associated with the formation of each partial product. This elimination is made possible by restricting the recoded multiplier digits to 0, ±1, or ±2, only, effectively eliminating the need for multiplication by ±3. These two features lead to high-speed area-efficient SB multiplication suitable for modern high-performance VLSI and ASIC implementations.

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