Signal-to-noise-plus-distortion Ratio Research Articles

A 13b 600-675MS/s Tri-State Pipelined-SAR ADC With Inverter-Based Open-Loop Residue Amplifier

This article presents a 13-b high-speed pipelined-successive-approximation-register (pipelined-SAR) analog-to-digital converter (ADC). By utilizing the comparator metastability, a tri-state SAR logic is introduced to achieve a fast approximation process. The tri-state SAR outputs three states by one comparator after each comparison cycle, and the effective-number-of-bits (ENOBs) can improve up to 1 b when the metastability boundary is set at ±1/4 LSB. In addition, an open-loop inverter-based residue amplifier (RA) is proposed with simple circuit implementation. The RA gain is well defined by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula> ratio and is immune to process, voltage, and temperature (PVT) variations. Fabricated in 40-nm CMOS technology, the prototype ADC achieves a mean signal-to-noise plus distortion ratio (SNDR) of 59.8–62.8 dB, with 1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma $ </tex-math></inline-formula> than 1.7 dB, at 600–625 MS/s over −40° to 125° temperature range and 1.1–1.2 V power supply range, a 67 dB dynamic range (DR), and a 62.4 dB SNDR for a Nyquist input while sampling at 625 MS/s. The overall power consumption is 7.05 mW.

An Energy-Efficient SAR ADC With a Coarse-Fine Bypass Window Technique

This paper presents a coarse-fine bypass window technique to improve the energy efficiency of the successive approximation register (SAR) analog-to-digital converter (ADC) by skipping unnecessary conversion cycles when the input signal is within the bypass windows. It utilizes the time information of the MSB comparison to coarsely detect the input range without a dedicated timing budget. Based on the coarse detection results, the fine bypass window is configured by reusing the digital-to-analog converter (DAC) to accurately detect the input signal. Due to the presence of the coarse detection, the multi-window detection and its corresponding bypass operation are realized to maximize the effectiveness of the bypass window technique. In addition, the MSB-spilt switching scheme is proposed to reduce the DAC switch-back energy. A prototype 8-bit SAR ADC equipped with the proposed technique is fabricated in a 65-nm CMOS process. At a 350-MS/s sampling rate with a Nyquist input, the measured signal-to-noise-plus-distortion ratio (SNDR) and spurious-free dynamic ranges (SFDR) are 44.9 dB and 63.9 dB, respectively. At a supply voltage of 1.2 V, the ADC consumes power of 1.58 mW with the full-scale sinusoidal input signal. The ADC achieves an effective number of bits (ENOB) of 7.17 bit, resulting in a figure-of-merit (FoM) of 31.3 fJ/conversion-step. The ADC core occupies an active area of 0.0096 mm2.

A 16-bit 2.5-MS/s SAR ADC with on-chip foreground calibration

This article presents a 16-bit 2.5-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with on-chip foreground calibration, including two digital-to-analog converters (DACs). Apart from the traditional segmented capacitor DAC (CDAC) used in ADC, the assistant DAC (ADAC) is added to store errors, including offset and mismatch, and compensate them based on the calculation. The high-performance comparator and modified timings are used to meet the needs for speed and resolution while paralleling switches are applied to reduce the impacts of charge injection. The proposed SAR ADC has been designed and fabricated in a 55 nm CMOS process with an area of 0.76 mm2. The 81.51 dB signal to noise-plus-distortion ratio (SNDR) and the 96.8 dB spurious-free dynamic range (SFDR) are measured at 2.5 MS/s respectively, while the integral nonlinearity (INL) is ＋2.4/−1.7 LSB. The core ADC consumes 25.8 mW power under 3.3 V analog supply and 1.2 V digital supply with the Schreier figure-of-merit (FOMs) 159.8 dB.

A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations

This brief presents a 12-bit successive approximation register (SAR)-based time-interleaved (TI) analog-to-digital converter (ADC) with a fully programmable interleaving factor. A total of six SAR sub-ADCs can be time-interleaved. The interleaving factor is programmable from 2 to 6, resulting in an overall sampling rate from 300 to 900MS/s. On-chip offset, gain, and timing skew background calibrations allow reducing the interleaving spurs to less than −73dBc in every configuration. In particular, the proposed difference-based skew calibration efficiently operates in any configuration, not being limited to power-of-2 interleaving factors. Fabricated in a 28-nm bulk CMOS process, the presented TI-ADC achieves a Nyquist-frequency signal-to-noise plus distortion ratio (SNDR) and a spurious-free dynamic range (SFDR) of 52.01dB and 58.82dBc at 900MS/s, respectively, with an active area occupation of 0.48 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\mathbf {2}}$ </tex-math></inline-formula> and similar metrics across all the configurations. Featuring a power dissipation of 42.96mW at 900MS/s, the Nyquist-frequency Schreier figure of merit (FoM) is 152.2dB, whereas the Walden one is 146.6fJ/Conv-step.

A parasitic elimination bootstrapped switch and a fast settling residual amplifier for high-speed and high-resolution pipelined ADC

This letter proposes a parasitic elimination bootstrapped switch and a fast settling residual amplifier to be used in multiplying digital-to-analog converter (MDAC) in order to improve the performance of pipelined ADC at high frequency. The parasitic elimination bootstrapped switch improves the sampling spurious free dynamic range (SFDR) by more than 6dB by shielding the nonlinear parasitic capacitance of the MOS transistor substrate. In addition, at high frequency, the negative zero point introduced by the later stage switch-capacitor circuit (which is easy to be ignored) will seriously deteriorates the settling time of residual amplifier in the former stage. A new zero-pole elimination technique is proposed, which greatly reduces the settling time of residual amplifier by nearly 11% and further improve the performance of MDAC. Simulated in 28nm CMOS technology, as the input signal is 1.38GHz, the former stage of the pipelined ADC implements high-speed high-resolution to obtain a SFDR of 75.77dB and a signal-to-noise-plus-distortion ratio (SNDR) of 68.05dB at a sampling frequency of 2.2GS/s.

Closed-form MSE and achievable rate for indirect learning DPD

The digital pre-distortion (DPD) signal processing is an effective way to mitigate the power amplifier (PA) nonlinearity effect. For communication systems containing DPD and PA, it is difficult to acquire performance metrics closed-forms for any DPD architecture since there was no mathematical expression for each DPD coefficient. Usually, researchers look for more efficient DPD algorithms for DPD coefficients (compared to the existing ones) in terms of computational complexity, delay, power consumption, etc. Consequently, the performance is evaluated through intensive simulation. In this paper, we show how one can exploit the results of our recent work to mathematically model the indirect learning architecture (ILA) DPD and efficiently derive important measures in communication systems, e.g. normalized mean square error (NMSE), achievable rate, and signal-to-noise plus distortion ratio (SNDR). The author would like to clarify that this work might be the first one to provide closed-form analysis for DPD systems. We think the provided framework/analysis will open the door to other researchers/engineers to plug their own assumptions and derive the performance metrics. The derived expressions of the performance metrics (NMSE, SNDR, and achievable rate) are validated through Monte Carlo simulations. We also derive a closed-form expression for the achievable rate bound for the transmit chain. Moreover, we analytically study the effect of the thermal noise and the quantization noise, in the analog-digital conversion (ADC) process, on the NMSE and achievable rate. The analytical expressions are validated through numerical simulations.

Performance and Optimization of Reconfigurable Intelligent Surface Aided THz Communications

TeraHertz (THz) communications can satisfy the high data rate demand with massive bandwidth. However, severe path attenuation and hardware imperfection greatly alleviate its performance. Therefore, we utilize the reconfigurable intelligent surface (RIS) technology and investigate the RIS-aided THz communications. We first prove that the small-scale amplitude fading of THz signals can be accurately modeled by the fluctuating two-ray distribution based on two THz signal measurement experiments conducted in a variety of different scenarios. To optimize the phase-shifts at the RIS elements, we propose a novel swarm intelligence-based method that does not require full channel estimation. We then derive exact statistical characterizations of end-to-end signal-to-noise plus distortion ratio (SNDR) and signal-to-noise ratio (SNR). Moreover, we present asymptotic analysis to obtain more insights when the SNDR or the number of RIS&#x2019;s elements is high. Finally, we derive analytical expressions for the outage probability and ergodic capacity. The tight upper bounds of ergodic capacity for both ideal and non-ideal radio frequency chains are obtained. It is interesting to find that increasing the number of RIS&#x2019;s elements can significantly improve the THz communications system performance. For example, the ergodic capacity can increase up to 25&#x0025; when the number of elements increases from 40 to 80, which incurs only insignificant costs to the system.

A 3rd-Order FIR Filter Implementation Based on Time-Mode Signal Processing

This paper presents the hardware implementation of a 3rd-order low-pass finite impulse response (FIR) filter based on time-mode signal processing circuits. The filter topology consists of a set of novel building blocks that perform the necessary functions in time-mode including z−1 operation, time addition and time multiplication. The proposed time-mode low-pass FIR filter was designed in a 28 nm Samsung fully-depleted silicon-on-insulator FD-SOI process under 1 V supply voltage with 5 MHz sampling frequency. Simulation results validate the theoretical analysis. The FIR filter achieves a signal-to-noise-plus-distortion ratio (SNDR) of 38.6 dB at the input frequency of 50 KHz consuming around 200 μW.

A Timing Mismatch Background Calibration Algorithm With Improved Accuracy

This brief presents a novel timing mismatch background calibration algorithm for time-interleaved (TI) analog-to-digital converters (ADCs). It can calibrate an arbitrary number of channels with an arbitrary input frequency. It also increases the calibration accuracy by applying the autocorrelation functions with an expanded interval. Besides, the proposed algorithm effectively prevents the small derivative values in the correlation difference from degrading the skew estimation accuracy. Compared to prior works on calibration, this work has at least five times better detection accuracy when the frequency of the input signal is close to the Nyquist frequency. This is without the need for calculating the high-order statistics. Finally, we simulate a four-channel 12-bit TI ADC with non-ideal effects added. Simulation results show that the proposed algorithm increases the signal to noise-plus-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) from 35.5 and 40.0 dB to 63.3 and 84.6 dB, respectively, when the input frequency is close to the Nyquist frequency.

A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC Using a Simultaneous Capacitor and Op-amp Sharing Technique

This work presents a low-power 10-bit 40 MSPS Pipelined ADC with 1.8V supply voltage in a 180nm silicon-based CMOS process. Simultaneous capacitor sharing and op-amp sharing technique is used between two successive stages of a Sample-and-Hold Amplifier (SHA) to reduce the power consumption. The memory effect in the proposed ADC is eliminated by a low input capacitance variable gm op-amp. The differential and integral nonlinearity of the converter is within LSB. Simulation results show that the required Signal-Furious-Dynamic range (SFDR) of 70dB, Signal-to -Noise-plus Distortion Ratio (SNDR) of 56.1dB and 9.02 Effective Number of Bits ( ENOB ) has been achieved with a 2 MHz, 1-Vp−p, diff input signal while consuming only 7.3mW power from 1.8V supply.

A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems

A single-channel reconfigurable successive approximation register (SAR) analog-to-digital converter (ADC) is presented, which features its speed expanding with conversion mode. The reconfigurable capacitor digital to analog converter (CDAC) is proposed to achieve multiple conversion modes without wasting capacitance. In 1-b/cycle conversion mode, the proposed ADC can achieve the sampling rate of 60-Ms/s and 9-b resolution. Based on the 2-b/cycle conversion mode, the proposed ADC can double the sampling rate and be reconfigured as a 120-MS/s, 8-b converter. Besides, the detection skip algorithm and charge sharing technology are involved to remove the precharge operation time and reduce the switching energy consumption. Moreover, the control logic is optimized to minimize the chip area and matches the reconfigurable characteristics well. A prototype ADC is fabricated in the 180-nm standard CMOS process, which achieves the 54.1-/46.7-dB signal-to-noise-plus-distortion ratio (SNDR) at 60-/120-MHz sampling frequency with the power consumption of 1.9/3.5 mW. The prototype ADC achieves a peak figure of merit (FoM) of 77-fJ/Conv.step at 2-b/cycle conversion mode. The ADC core occupies an active area of only 0.12 mm2.

A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier

This paper presents a process, voltage, and temperature (PVT)-insensitive dynamic amplifier (DA) with gain enhancement for a pipelined successive approximation register (SAR) analog-to-digital converter (ADC). The gain shift due to temperature and process variation is attenuated through the counteraction of input transconductance and delay-based integration time. Furthermore, based on charge conservation, a gain-folding technique is proposed to improve the gain limit of conventional DA, tripling the gain amplitude. The proposed DA is incorporated in a design of a 12-bit 100 MS/s SAR ADC. In 65 nm CMOS process, at 100 MS/s, the prototype ADC achieves an SNDR (signal-to-noise plus distortion ratio) of 65.7 dB and a Walden FoM of 12.06 fJ/conversion-step for a near-Nyquist input. The power dissipation is less than 1.9 mW. No more than 1.65 dB SNDR variations are obtained for supply voltage varying from 1.15 to 1.25 V and temperature varying from −20 °C to 125 °C with various process corners, respectively.

Analysis of DF Relay Selection in Massive MIMO Systems With Hardware Impairments

We consider a massive multiple-input multiple-output (m-MIMO) system in which a source communicates with a destination with the help of multiple single-antenna decode-and-forward (DF) relays. Employing optimal relay selection, we analyze the system performance in presence of hardware impairments (HWI) for two m-MIMO scenarios: massive-antenna source and single-antenna destination (m-MIMO I), and massive-antenna source and destination (m-MIMO II). We obtain lower bounds on the average signal-to-noise plus distortion ratio (SNDR) of the system and show that in the m-MIMO II regime, the HWI levels at the relays become the only limiting factors. Employing extreme value theory, we demonstrate that as the number of relays increases the end-to-end SNDR of the system tends to Gumbel and Weibull distributions for the m-MIMO I and m-MIMO II systems, respectively. In addition, for both arbitrary numbers of source and destination antennas and m-MIMO scenarios, we provide closed form expressions for optimal power allocation between the source and the selected relay, and the effects of HWI level distributions between the receiving and the transmitting parts of the relay (which can be exploited for optimal system design under cost constraints).

A Power-Efficient Pipelined ADC with an Inherent Linear 1-Bit Flip-Around DAC

An unity-gain 1-bit flip-around digital-to-analog converter (FADAC), without any capacitor matching issue, is proposed as the front-end input stage in a pipelined analog-to-digital converter (ADC), allowing an input signal voltage swing up to be doubled. This large input swing, coupled with the inherent large feedback factor (ideally β = 1) of the proposed FADAC, enables a power-efficient low-voltage high-resolution pipelined ADC design. The 1-bit FADAC is exploited in a SHA-less and opamp-sharing pipelined ADC, exhibiting 12-bit resolution with an input swing of 1.8 Vpp under a 1.1 V power supply. Fabricated in a 0.13-μm CMOS process, the prototype ADC achieves a measured signal-to-noise plus distortion ratio (SNDR) of 66.4 dB and a spurious-free dynamic range (SFDR) of 76.7 dB at 20 MS/s sampling rate. The ADC dissipates 5.2 mW of power and occupies an active area of 0.44 mm2. The measured differential nonlinearity (DNL) is +0.72/−0.52 least significant bit (LSB) and integral nonlinearity (INL) is +0.84/−0.75 LSB at a 3-MHz sinusoidal input.

How Much do Hardware Imperfections Affect the Performance of Reconfigurable Intelligent Surface-Assisted Systems?

In the present work, we investigate the impact of transceiver hardware imperfection on reconfigurable intelligent surface (RIS)-assisted wireless systems. In this direction, first, we present a general model that accommodates the impact of the transmitter (TX) and receiver (RX) radio frequency impairments. Next, we derive novel closed-form expressions for the instantaneous end-to-end signal-to-noise-plus-distortion-ratio (SNDR). Building upon these expressions, we extract an exact closed-form expression for the system's outage probability, which allows us not only to quantify RIS-assisted systems' outage performance but also reveals that the maximum allowed spectral efficiency of the transmission scheme is limited by the levels of the transceiver hardware imperfection. Likewise, a diversity analysis is provided. Moreover, in order to characterize the capacity of RIS-assisted systems, we report a new upper-bound for the ergodic capacity, which takes into account the number of the RIS's reflective units (RUs), the level of TX and RX hardware imperfection, as well as the transmission signal-to-noise-ratio (SNR). Finally, two insightful ergodic capacity ceilings are extracted for the high-SNR and high-RUs regimes. Our results highlight the importance of accurately modeling the transceiver hardware imperfection and reveals that they significantly limit the RIS-assisted wireless system performance.

A 2.64- μW 71-dB SNDR Discrete-Time Signal-Folding Amplifier for Reducing ADC's Resolution Requirement in Wearable ECG Acquisition Systems.

This paper presents the design of a low-power discrete-time signal-folding amplifier intended for use in place of programmable-gain amplifiers (PGA) in electrocardiogram (ECG) acquisition systems. The amplifier provides a fixed high gain while preventing output signal saturation even with rail-to-rail inputs, thanks to the proposed discrete-time signal folding technique; the fixed gain eliminates the need of gain-control circuitry while the high gain helps relax the resolution requirement of the analog-to-digital converter (ADC) that follows, thus resulting in lower power consumption and design complexity for the ADC. Fabricated in a standard 0.18- μm CMOS process, the amplifier occupies an active area of 0.254 mm2 and consumes 2.64 μW from a 1.2-V supply voltage. While amplifying a rail-to-rail input (2.4 Vpp differential) with a gain of 17.8V/V, the amplifier achieves a signal-to-noise-plus-distortion ratio (SNDR) of 71dB, thus making it very attractive for high-fidelity ECG recording amid large input interferences.

Single low‐gain amplifier compensated hybrid delta‐sigma modulator

This article presents low-power circuit design techniques to achieve third-order noise shaping by employing multiple stages of passive switched-capacitor gain-boosted integrator and a passive switched-capacitor integrator. First integrator is a passive switched-capacitor for higher linearity. Second integrator is a three-stage passive switched-capacitor gain-boosted integrator to provide passive gain to the loop filter as well as the second DAC feedback. While the third integrator is a two-stage passive switched-capacitor gain-boosted integrator to provide passive gain as well as third DAC feedback for higher stability. Multiple lower stages of passive switched-capacitor gain-boosted integrators employed to enhance the noise shaping order of the modulator and suppress the parasitic effect. The preamplifier is the only active block, while the dynamic comparator used as single-bit quantiser. The complete transistor level with thermal noise simulation can achieve 84 dB of dynamic range (DR), 78.2 dB signal-to-noise-plus-distortion ratio (SNDR), and 78.5 dB signal-to-noise ratio (SNR) for 500 Hz signal bandwidth. It can also achieve signal-to-spurious-free dynamic range (SFDR) of 78.2 dB with estimated power consumption of 220 nW at 1 V supply voltage in SMIC 28 nm CMOS Technology. Finally, it can achieve state-of-the-art Walden Figure-of- Merit (FoM W ) of 33 fJ/Conv-Step and Schreier FoM S of 171.2 dB.

A 5-MHz bandwidth 78.1-dB SNDR 2-2 MASH delta-sigma modulator

ABSTRACTThis paper presents a 4-bit, 2–2 multi-stage noise shaping (MASH) delta-sigma modulator (DSM) fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) process. The DSM was designed using a cascade-of-integrators with a feedforward (CIFF) structure. The first integrator was designed to reduce the loading effect of the system’s front-end circuit using a switched-resistor integrator instead of the conventional switched-capacitor method. The CIFF structure requires an active adder, which is generally implemented with a high-bandwidth high-swing amplifier. In this paper, the active adder is eliminated and an adder-less integrator is implemented in the MASH DSM. The DSM prototype has an over-sampling ratio (OSR) of 16 and a 160 MHz sampling frequency. The prototype’s measured signal-to-noise ratio (SNR) is 82.4 dB and the signal-to-noise-plus-distortion ratio (SNDR) is 78.1 dB for a signal bandwidth of 5 MHz. The measured total power consumption is 26 mW at a 1.8 V supply voltage, and the chip core size is 0.67 mm2. The energy required per conversion step is 0.4 pJ/conv.

A 1-V 175-$\mu$ W 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques

A 2-1 multistage noise-shaping (MASH) switched-capacitor (SC) delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. We developed two separate segmented integration techniques to implement the first two integrators in the DSM. The techniques use both an inverter (IVT)-based opamp and a source-coupled-pair (SCP)-based opamp to relay the charge integration operation. This increases performance while saving power. The first integrator also operates more slowly during output sampling to further reduce power consumption. Operating at a 5-MS/s sampling rate, this chip consumes 175 $\mu \text{W}$ from a 1-V supply. For a 25-kHz signal bandwidth, it achieves a 96.1-dB signal-to-noise ratio (SNR), a 94.6-dB signal-to-noise-plus-distortion ratio (SNDR) and a 98.5-dB dynamic range (DR). Its active area is $1.13\times 0.34\,\,\text {mm}^{2}$ .

A 0.4-V 10-bit 10-KS/s SAR ADC in 0.18 μm CMOS for low energy wireless senor network chip

A 10-bit 10-KS/s asynchronous successive approximation register (SAR) analogue-to-digital converter (ADC) in 180 nm CMOS process is proposed for low energy wireless senor network chip. Nanowatt power consumption magnitude can be achieved benefiting from the novel switch scheme which can reduce the average switching energy and area of the capacitive digital-to-analog converter (DAC) by 97.66% and 50% without reset energy compared to the conventional approach, respectively. Meanwhile, a cascode current is employed in the subthreshold dynamic comparator to suppress the total offset voltage (mean+3std) variation with the bulk-driven differential pair. As a consequence, the fluctuation of total offset voltage is only 0.28 mV when the input common-mode voltage operates from 200 mV up to 400 mV at 0.4 V supply. Simulation results indicate that a signal-to-noise-plus-distortion ratio (SNDR) of 58.75 dB and a power consumption of 30.4 nW can be achieved at 0.4 V supply voltage and a near Nyquist rate input, resulting in Walden's figure-of-merit (FOMw) of 4.32fJ/conversion-step.