Abstract
This paper presents the hardware implementation of a 3rd-order low-pass finite impulse response (FIR) filter based on time-mode signal processing circuits. The filter topology consists of a set of novel building blocks that perform the necessary functions in time-mode including z−1 operation, time addition and time multiplication. The proposed time-mode low-pass FIR filter was designed in a 28 nm Samsung fully-depleted silicon-on-insulator FD-SOI process under 1 V supply voltage with 5 MHz sampling frequency. Simulation results validate the theoretical analysis. The FIR filter achieves a signal-to-noise-plus-distortion ratio (SNDR) of 38.6 dB at the input frequency of 50 KHz consuming around 200 μW.
Highlights
In many modern integrated circuit applications, better speed and lower power consumption are important criteria
The finite impulse response (FIR)/IIR counterpart implementations in time-mode require the basic operators to work in time domain which means that z−1, adders [4,7,8] and multipliers [9,10] must be able to handle time-mode quantities [11]
Our work proposes the implementation of a 3rd order sampled-data low pass timemode FIR filter which is based on the novel time-mode multiplier and time-mode adder
Summary
In many modern integrated circuit applications, better speed and lower power consumption are important criteria. The FIR/IIR counterpart implementations in time-mode require the basic operators to work in time domain which means that z−1, adders [4,7,8] and multipliers [9,10] must be able to handle time-mode quantities [11]. These systems are categorized as discretetime/continuous signal processing (DT-CSP) systems [12]. Our work proposes the implementation of a 3rd order sampled-data low pass timemode FIR filter which is based on the novel time-mode multiplier and time-mode adder. Both circuits are based on the modification of a simple time register topology [15,16].
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