A 2.64- μW 71-dB SNDR Discrete-Time Signal-Folding Amplifier for Reducing ADC's Resolution Requirement in Wearable ECG Acquisition Systems.

Abstract

This paper presents the design of a low-power discrete-time signal-folding amplifier intended for use in place of programmable-gain amplifiers (PGA) in electrocardiogram (ECG) acquisition systems. The amplifier provides a fixed high gain while preventing output signal saturation even with rail-to-rail inputs, thanks to the proposed discrete-time signal folding technique; the fixed gain eliminates the need of gain-control circuitry while the high gain helps relax the resolution requirement of the analog-to-digital converter (ADC) that follows, thus resulting in lower power consumption and design complexity for the ADC. Fabricated in a standard 0.18- μm CMOS process, the amplifier occupies an active area of 0.254 mm2 and consumes 2.64 μW from a 1.2-V supply voltage. While amplifying a rail-to-rail input (2.4 Vpp differential) with a gain of 17.8V/V, the amplifier achieves a signal-to-noise-plus-distortion ratio (SNDR) of 71dB, thus making it very attractive for high-fidelity ECG recording amid large input interferences.