Signal Processing Architecture Research Articles

FPGA-Based High-Speed Energy-Efficient 32-Bit Fixed-Point MAC Architecture for DSP Application in IoT Edge Computing

Designing high-speed and energy-efficient blocks for image and digital signal processing (DSP) architecture is an evolving research field. This work designs a high-speed and energy-efficient multiply-accumulate (MAC) unit to augment the performance of field-programmable gate array (FPGA)-based accelerators and softcore processors. In this work, three discrete 32-bit fixed-point signed MAC architectures were designed in Verilog and synthesized for the Zynq 7000 ZedBoard to obtain efficient MAC architecture. The ultimate goal of this work is to design a fast and energy-efficient MAC unit that can achieve speed up to the DSP48 block to reduce the latency of IoT edge computing. Energy efficiency was achieved in PPG and partial product addition (PPA) for the proposed Booth radix-4 Dadda (BR4D)-based MAC. At PPG, the width of the partial product (PP) terms was optimized with Bewick’s signed extension to reduce the power consumption. At PPA, the number of PP rows reduces the critical path delay (CPD) with Dadda-based PPA. The proposed BR4D MAC unit offers a reduction in dynamic power, CPD, power-delay product (PDP) and energy-delay product (EDP) by 22%, 9%, 29% and 36%, respectively, compared to standard Booth radix-4 Wallace tree (BR4WT) based MAC. Furthermore, hybrid MACs (BR4WT and BR4D) were compared with the current state-of-the-art (SoA) designs, and it was found that the proposed BR4D MAC is 47% faster compared to the same design in SoA. The proposed BR4D was tested for frequency scaling technique by reducing the frequency in steps of 10 MHz from a maximum usable frequency (MUF) of 64 MHz to 10 MHz to evaluate the performance for low-power applications. Reducing clock frequency by 84% will reduce the power consumption at the same proportion and speed by 38%. Additionally, the proposed design helps to improve the battery life of IoT end nodes with a reduction in energy consumption and EDP by 76% and 61%, respectively.

Short-term load forecasting method of IES based on RLA neural network with dual signal processing

Significant fluctuations and strong nonlinearity in integrated energy system data pose challenges to the precision of multi-energy load forecasting. To address this issue, the present study proposes a residual network (ResNet) - long short-term memory (LSTM) with an attention neural network model founded on a dual signal processing architecture. Initially, the dual signal processing framework was introduced to overcome the limitations of classical signal decomposition, particularly its inability to effectively mitigate high-frequency noise. This approach moderates the nonstationary attributes of the initial data and furnishes comprehensive information for the subsequent predictive model. Subsequently, the study employs the ResNet model for spatial feature extraction and the LSTM model for temporal feature extraction to augment the efficiency and precision in identifying multi-energy load characteristics. An attention mechanism is further integrated to allocate weights to diverse load features, thereby optimizing data transfer processing. The experimental results confirm that the proposed model offers superior adaptability to the integrated energy systems environment and substantially minimizes prediction errors in comparison to alternative models.

Auditory-inspired adaptive frequency tracking

One of the best frequency trackers to date is the human (mammalian) auditory system, which has evolved through millions of years of resolving classification problems. It is a versatile, elegant and powerful sound processing unit. It excels in detecting, estimating, and classifying multiple targets simultaneously even in noisy environments. Hence, mimicking even some features of the auditory system could be beneficial in developing superior frequency tracking and classification algorithms. An auditory inspired adaptive synchrony capture filterbank (SCFB) signal processing architecture for tracking signal frequency components was proposed in a related paper [JASA-2013]. The SCFB architecture consists of a fixed array of traditional, passive linear, gammatone filters in cascade with a bank of three adaptively tunable bandpass filters that form a frequency-discriminator-loop (FDL). The SCFB exhibits many desirable properties for processing speech, music, and other complex sounds. In recent work [Dec2021], the algorithm was modified using adaptive tuning parameters, and a generalized way to determine/suppress voiced and unvoiced (silent) regions. This modified algorithm estimates frequencies with higher accuracy even in the presence of closely spaced input tones. Preliminary analysis with synthetic, human speech and humpback/whale-call signals demonstrates that the revised algorithm performs well. This talk will focus on follow-on work.

Design of ultra-wideband pulsar signal acquisition and processing architecture and functional verification

Design of ultra-wideband pulsar signal acquisition and processing architecture and functional verification

Parameter estimation of the systems with irregularly missing data by using sequentially parallel distributed adaptive signal processing architecture

This paper considers problems related to output error models for output data estimation and parameter identification in missing output data systems. In this regard, a new sequentially parallel distributed adaptive signal processing method with the implementation of a low complexity least squares algorithm is introduced to estimate the parameters of an auxiliary model relative to the original system, as well as handling irregularly missing output data in a stochastic framework. The validation of the proposed distributed architecture using the low complexity least squares algorithm is presented in terms of computational complexity and processing time. Measurement results show that the proposed architecture using the low complexity least squares approach provides fast convergence, parallel linear computational complexity, and significantly reduced processing time compared to the sequentially operated recursive least square (RLS) algorithm for parameter identification in missing output data systems. Finally, the effectiveness of the low complexity least squares algorithm is tested with a system example

Pseudolite Multipath Estimation Adaptive Mitigation of Vector Tracking Based on Ref-MEDLL

Among many indoor positioning technologies, pseudolite positioning technology has become an important supplement to GNSS. In indoor open environments, pseudolite positioning technology can usually perform high-precision positioning. However, in a complex environment, the pseudolite receiver is seriously interfered by multipath and other interference signals, which will lead to a serious decline in the observation accuracy, signal lock loss or even no positioning results. Therefore, this work proposes a pseudolite indoor anti-multipath receiver based on reference multipath estimating delay lock loop (Ref-MEDLL). It adds the Ref-MEDLL multipath estimator module and the multipath mitigation module to the traditional receiver signal processing architecture. In the multipath mitigation module, the multipath estimation adaptive mitigation of vector tracking (MEAM-VT) method and the multipath estimation direct mitigation (MEDM) method for multipath mitigation is proposed. Experimental results show that the Ref-MEDLL multipath estimation method has good adaptability to multipath signals that have different time delays and different amplitudes; both the MEDM receiver and the MEAM-VT receiver have good multipath mitigation performance. The MEAM-VT method performs better than the MEDM method in multipath mitigation and tracking, but the stability of the pseudorange observations of the MEAM-VT method is not as good as that of the MEDM method. The positioning accuracy of the MEDM receiver and the MEAM-VT receiver has been improved to different degrees in static positioning experiments and dynamic positioning experiments.

Wideband Array Signal Processing with Real-Time Adaptive Interference Mitigation.

Wideband beamforming and interference cancellation for phased array antennas requires advances in signal processing algorithms, software, and specialized hardware platforms. A high-throughput array receiver has been developed that enables communication in radio frequency interference-rich environments with field programmable gate array (FPGA)-based frequency channelization and packetization. In this study, a real-time interference mitigation algorithm was implemented on graphics processing units (GPUs) contained in the data pipeline. The key contribution is a hardware and software pipeline for subchannelized wideband array signal processing with 150 MHz instantaneous bandwidth and interference cancellation with a heterogeneous, distributed, and scaleable digital signal processing (DSP) architecture that achieves 30 dB interferer cancellation null depth in real time with a moving interference source.

Adaptive parallel decision deep neural network for high-speed equalization.

The equalization plays a pivotal role in modern high-speed optical wire-line transmission. Taking advantage of the digital signal processing architecture, the deep neural network (DNN) is introduced to realize the feedback-free signaling, which has no processing speed ceiling due to the timing constraint on the feedback path. To save the hardware resource of a DNN equalizer, a parallel decision DNN is proposed in this paper. By replacing the soft-max decision layer with hard decision layer, multi-symbol can be processed within one neural network. The neuron increment during parallelization is only linear with the layer count, rather than the neuron count in the case of duplication. The simulation results show that the optimized new architecture has competitive performance with the traditional 2-tap decision feedback equalizer architecture with 15-tap feed forward equalizer at a 28GBd, or even 56GBd, four-level pulse amplitude modulation signal with 30dB loss. And the training convergency of the proposed equalizer is much faster than its traditional counterpart. An adaptive mechanism of the network parameter based on forward error correction is also studied.

High-Throughput Single-Molecule Sensors: How Can the Signals Be Analyzed in Real Time for Achieving Real-Time Continuous Biosensing?

Single-molecule sensors collect statistics of single-molecule interactions, and the resulting data can be used to determine concentrations of analyte molecules. The assays are generally end-point assays and are not designed for continuous biosensing. For continuous biosensing, a single-molecule sensor needs to be reversible, and the signals should be analyzed in real time in order to continuously report output signals, with a well-controlled time delay and measurement precision. Here, we describe a signal processing architecture for real-time continuous biosensing based on high-throughput single-molecule sensors. The key aspect of the architecture is the parallel computation of multiple measurement blocks that enables continuous measurements over an endless time span. Continuous biosensing is demonstrated for a single-molecule sensor with 10,000 individual particles that are tracked as a function of time. The continuous analysis includes particle identification, particle tracking, drift correction, and detection of the discrete timepoints where individual particles switch between bound and unbound states, yielding state transition statistics that relate to the analyte concentration in solution. The continuous real-time sensing and computation were studied for a reversible cortisol competitive immunosensor, showing how the precision and time delay of cortisol monitoring are controlled by the number of analyzed particles and the size of the measurement blocks. Finally, we discuss how the presented signal processing architecture can be applied to various single-molecule measurement methods, allowing these to be developed into continuous biosensors.

Radar Signal Processing Architecture for Early Detection of Automotive Obstacles

With the mass adoption of automotive vehicles, road accidents have become a common occurrence. One solution to this problem is to employ safety systems that can provide early warning for potential accidents. These systems alert drivers to brake or take active control of a vehicle in order to make braking safer and smoother, thereby protecting drivers and all other road traffic participants. Most such safety systems utilize millimeter-wave radar as primary sensors, and one of the main challenges is real-time data processing from multiple sensors integrated into a single passenger car. When an obstacle is too close to a vehicle, often there is insufficient time to run higher-order digital signal processing algorithms; hence, the decision to brake must be made based on low-level hardware processing only. For that purpose, a hardware generator for the early detection of automotive obstacles that does not impede the operation of higher-order signal processing algorithms is described. The proposed generator is captured in the Chisel hardware design language and a method for reducing the overall ranging latency is presented. The system constraints are calculated using an exemplary radar front-end and the proposed generator parameters. The obtained analytical results are experimentally confirmed with a prototype composed of a typical industrial radar front-end while the signal processing back-end instance of the described generator was implemented on an FPGA board. The measurements demonstrate that with the fast proximity alert, objects can be detected in less than a hundred microseconds, thus considerably reducing the system reaction delay and braking distance.

Electromyography Monitoring Systems in Rehabilitation: A Review of Clinical Applications, Wearable Devices and Signal Acquisition Methodologies

Recently, there has been an evolution toward a science-supported medicine, which uses replicable results from comprehensive studies to assist clinical decision-making. Reliable techniques are required to improve the consistency and replicability of studies assessing the effectiveness of clinical guidelines, mostly in muscular and therapeutic healthcare. In scientific research, surface electromyography (sEMG) is prevalent but underutilized as a valuable tool for physical medicine and rehabilitation. Other electrophysiological signals (e.g., from electrocardiogram (ECG), electroencephalogram (EEG), and needle EMG) are regularly monitored by medical specialists; nevertheless, the sEMG technique has not yet been effectively implemented in practical medical settings. However, sEMG has considerable clinical promise in evaluating muscle condition and operation; nevertheless, precise data extraction requires the definition of the procedures for tracking and interpreting sEMG and understanding the fundamental biophysics. This review is centered around the application of sEMG in rehabilitation and health monitoring systems, evaluating their technical specifications, including wearability. At first, this study examines methods and systems for tele-rehabilitation applications (i.e., neuromuscular, post-stroke, and sports) based on detecting EMG signals. Then, the fundamentals of EMG signal processing techniques and architectures commonly used to acquire and elaborate EMG signals are discussed. Afterward, a comprehensive and updated survey of wearable devices for sEMG detection, both reported in the scientific literature and on the market, is provided, mainly applied in rehabilitation training and physiological tracking. Discussions and comparisons about the examined solutions are presented to emphasize how rehabilitation professionals can reap the aid of neurobiological detection systems and identify perspectives in this field. These analyses contribute to identifying the key requirements of the next generation of wearable or portable sEMG devices employed in the healthcare field.

Auditory-inspired adaptive frequency tracking

One of the best frequency trackers to date is the human (mammalian) auditory system, which has evolved through millions of years of resolving classification problems. It is a versatile, elegant and powerful sound processing unit. It excels in detecting, estimating, and classifying multiple targets simultaneously even in noisy environments. Hence, mimicking even some features of the auditory system could be beneficial in developing superior frequency tracking and classification algorithms. An auditory inspired adaptive synchrony capture filterbank (SCFB) signal processing architecture for tracking signal frequency components was proposed in a related paper [JASA (2013)]. The SCFB architecture consists of a fixed array of traditional, passive linear, gammatone filters in cascade with a bank of three adaptively tunable bandpass filters that form a frequency-discriminator-loop (FDL). The SCFB exhibits many desirable properties for processing speech, music, and other complex sounds. In recent work (Dec 2021), the algorithm was modified using adaptive tuning parameters, and a generalized way to determine/suppress voiced and unvoiced (silent) regions. This modified algorithm estimates frequencies with higher accuracy even in the presence of closely spaced input tones. Preliminary analysis with synthetic, human speech and humpback/whale-call signals demonstrates that the revised algorithm performs well. This talk will focus on the latest updates.

Research on key technologies of multi-core DSP in smart substation redundancy network testing

Aiming at the network characteristics of a smart substation redundant network with complex communication messages, a large amount of interactive data, and high real-time performance, the test model of multiple submachines in a High-Availability Seamless Redundancy (HSR) loop network is analyzed. The requirements of packet types, size, and transmission speed are evaluated, and a hardware solution based on a multi-core Digital Signal Processor (DSP) and Parallel architecture FPGA is designed. The multi-core interaction strategy of DSP software and the multi-port high-speed communication method of FPGA are proposed, and the inter-core communication (IPC) interrupts and shared memory to achieve fast data migration between cores, based on the Serial RapidIO (SRIO) to complete high-speed message transmission. The throughput, delay, packet loss rate, and error frame detection functions are realized, tested, and verified, providing theoretical and practical support for the evaluation of redundant network performance of smart substations.

Real-time transponder architecture for hitless transmission baud rate switching in association with an auto-negotiation protocol

We propose a novel digital signal processing architecture for a coherent receiver that allows instantaneous and hitless variable baud rate transmission for integer sub-division values. This solution allows the receiver to self-adapt a new baud rate without processing modification, re-initialization, or any knowledge of the transmission speed modification. As for implantation concern, this architecture requires negligible extra logic compared to the standard one. Its development and operation developed on a simulation basis are presented; then its dynamic behavior and performance are demonstrated in a real-time experiment attesting a zero-bit loss. We also show how an in-line auto-negotiation protocol between a transmitter and a receiver minimizing the mediation through the control plane can leverage this instantaneous baud rate variation.

Exploiting the Properties of Reciprocal Filter in Low-Complexity OFDM Radar Signal Processing Architectures

Exploiting the Properties of Reciprocal Filter in Low-Complexity OFDM Radar Signal Processing Architectures

Validation of Parallel Distributed Adaptive Signal Processing (PDASP) Framework through Processing-Inefficient Low-Cost Platforms

The computational complexity of the multiple-input and multiple-output (MIMO) based least square algorithm is very high and it cannot be run on processing-inefficient low-cost platforms. To overcome complexity-related problems, a parallel distributed adaptive signal processing (PDASP) architecture is proposed, which is a distributed framework used to efficiently run the adaptive filtering algorithms having high computational cost. In this paper, a communication load-balancing procedure is introduced to validate the PDASP architecture using low-cost wireless sensor nodes. The PDASP architecture with the implementation of a multiple-input multiple-output (MIMO) based Recursive Least Square (RLS) algorithm is deployed on the processing-inefficient low-cost wireless sensor nodes to validate the performance of the PDASP architecture in terms of computational cost, processing time, and memory utilization. Furthermore, the processing time and memory utilization provided by the PDASP architecture are compared with sequentially operated RLS-based MIMO channel estimator on 2×2, 3×3, and 4×4 MIMO communication systems. The measurement results show that the sequentially operated MIMO RLS algorithm based on 3×3 and 4×4 MIMO communication systems is unable to work on a single unit; however, these MIMO systems can efficiently be run on the PDASP architecture with reduced memory utilization and processing time.

A memristor-based analogue reservoir computing system for real-time and power-efficient signal processing

Reservoir computing offers a powerful neuromorphic computing architecture for spatiotemporal signal processing. To boost the power efficiency of the hardware implementations of reservoir computing systems, analogue devices and components—including spintronic oscillators, photonic modules, nanowire networks and memristors—have been used to partially replace the elements of fully digital systems. However, the development of fully analogue reservoir computing systems remains limited. Here we report a fully analogue reservoir computing system that uses dynamic memristors for the reservoir layer and non-volatile memristors for the readout layer. The system can efficiently process spatiotemporal signals in real time with three orders of magnitude lower power consumption than digital hardware. We illustrate the capabilities of the system using temporal arrhythmia detection and spatiotemporal dynamic gesture recognition tasks, achieving accuracies of 96.6% and 97.9%, respectively. Our memristor-based fully analogue reservoir computing system could be of use in edge computing applications that require extremely low power and hardware cost.

On the Use of Reciprocal Filter Against WiFi Packets for Passive Radar

This article derives a novel unified signal processing scheme for WiFi-based passive radar in order to limit its complexity and enhance its suitability for short range civilian applications. To this purpose, the exploitation of a reciprocal filtering (RpF) strategy is investigated as an alternative to conventional matched filtering at the range compression stage. Along with the well-known advantage of a remarkable sidelobes control capability for the resulting range-Doppler response, the use of a RpF is shown to provide additional benefits for the specific sensor subject of this article. Specifically, it allows to streamline the disturbance cancellation stage and to implement a unified signal processing architecture which is capable to handle the different modulation schemes typically adopted in WiFi transmissions. Appropriate adjustments are also proposed to the theoretical RpF in order to cope with the inherent loss in terms of signal-to-noise power ratio. The effectiveness of the proposed signal processing scheme encompassing the RpF strategy is proved against both simulated and experimental datasets.

Resource-Saving Customizable Pipeline Network Architecture for Multi-Signal Processing in Edge Devices.

With the development of the information age, the importance of edge computing has been highlighted in industrial site monitoring, health management, and fault diagnosis. Among them, the processing and computing of signals in edge scenarios is the cornerstone of realizing these scenarios. While the performance of edge devices has been dramatically improved, the demand for signal processing in the edge side has also ushered in explosive growth. However, the deployment of traditional serial or parallel signal processing architectures on edge devices has problems such as poor flexibility, low efficiency, and low resource utilization, making edge devices unable to exert their maximum performance. Therefore, this paper proposes a resource-saving customizable pipeline network architecture with a space-optimized resource allocation method and a coordinate addressing method for irregular topology. This architecture significantly improves the flexibility of multi-signal processing in edge devices, improves resource utilization, and further increases the performance potential of edge devices. Finally, we designed a comparative experiment to prove that the resource-saving and customizable pipeline network architecture can significantly reduce resource consumption under the premise of meeting real-time processing requirements.

Guest Editorial: Special Issue on Design and Architectures for Signal and Image Processing 2021

Guest Editorial: Special Issue on Design and Architectures for Signal and Image Processing 2021