SiGe Technology Research Articles

A 2.5-V 56-mW baseband chain in a multistandard TV tuner for mobile and multimedia applications

This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process. A programmable 7th-order Chebyshev low pass filter with a calibration circuit is used in the analog baseband chain, and the programmable bandwidth is 1.8/2.5/3/3.5/4 MHz with an attenuation of 26/62 dB at offsets of 1.25/4 MHz. The baseband programmable gain amplifier can achieve a linear 40-dB gain range with 0.5-dB steps. Design trade-offs are carefully considered in designing the baseband circuit, and an automatic calibration circuit is used to achieve the bandwidth accuracy of 2%. ADC offset cancellation loop is also introduced to remove the offset from the layout and self-mixing, and the remaining offset voltage is only 1.87 mV Implemented in a 0.13-μm SiGe technology with a 0.6-mm2 die size, this baseband achieves IIP3 of 23.16 dBm and dissipates 22.4 mA under a 2.5-V supply.

Design of a transversal equalizer for electronic dispersion compensation in optical communication links

A programmable transversal equalizer for electronic dispersion compensation (EDC) in optical fiber communication systems is developed. Based on the SiGe technology with a cut-off frequency of 80 GHz, the equalizer consists of 6 seriesparallel amplifiers as delay units and 7 Gilbert variable gain amplifiers as taps, which ensure that the equalizer can work at the bit rate of 10 Gb/s. With different tap gains, the forward voltage gain of the transversal equalizer varies, which demonstrates that the equalizer has various filtering characteristics such as low pass filtering, band pass filtering, band reject filtering, and notch filtering, so it can effectively simulate the inverse transfer function of dispersive channels in optical communications, and can be used for compensating the inter-symbol interference and other nonlinear problems caused by dispersion. The equalizer (including pads) occupies an area of 0.40 mm×1.08 mm, and its total power dissipation is 400 mW with 3.3 V power supply.

60 GHz wide tuning range SiGe bipolar voltage controlled oscillator for high definition multimedia interface and wireless docking applications

A wide tuning range voltage controlled oscillator (VCO) with novel architecture is proposed in this work. The entire circuit consists of a VCO core, a summing circuit, a single-ended to differential (STD) converter and a buffer amplifier. The VCO core oscillates at half the desired frequency and the second harmonic of the VCO core is extracted by the summing circuit, which is then converted to a differential pair by the STD. The entire VCO circuit operates from 58.85 to 70.85 GHz with 20% frequency tuning range. The measured VCO gain is less than 1.6 GHz/V. The measured phase noise at 3 MHz offset is less than -78 dBc/Hz across the entire tuning range. The differential phase error of the output signals is measured by down converting the VCO output signals to low gigahertz frequency using an on-chip mixer. The measured differential phase error is less than 8°. The VCO circuit, which is constructed using 0.35 μm SiGe technology, occupies 770 × 550 μm 2 die area and consumes 62 mA under 3.5 V supply.

SPIROC (SiPM Integrated Read-Out Chip): dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

The SPIROC chip is a dedicated very front-end electronics for an ILC (International Linear Collider) prototype of hadronic calorimeter using Silicon photomultiplier (SiPM) or Multi-Pixel Photon Counters (MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2010. SPIROC is an evolution of FLC-SiPM used for the ILC Analogue HCAL physics prototype. The first prototype of SPIROC was submitted in June 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35 μm SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, dual gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2,000 photoelectron and the time with a 100 ps accurate Time-to-digital Converter (TDC). An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson Analogue-to-digital Converter (ADC) has been embedded to digitize the analogue memory content (time and charge on 2 gains). The data are then stored in a 4 Kbytes RAM. A very complex digital part has been integrated to manage all these features and to transfer the data to the DAQ which is described in Dulucq et al. After an exhaustive description, the extensive measurement results of this new front-end chip are presented.

Introduction to the Extreme Environment Technology and Reliability Special Issue

The five invited papers in this special issue cover some of the emerging topics in the present development and investigation of technologies and their reliability for applications under extreme environments. The first three papers focus on SiC, GaN, and SiGe technologies, respectively, followed by the fourth paper on microelectronics packaging reliability for high-temperature applications and the final paper on microelectronics and optoelectronics reliability for space applications.

Silicon-Germanium as an Enabling Technology for Extreme Environment Electronics

“Extreme environment” electronics represent an important niche market in the trillion dollar global electronics industry and span the operation of electronic circuits and systems in surroundings lying outside the domain of conventional commercial or military specifications. Such extreme environments might include, for instance, the following: 1) operation down to very low temperatures (e.g., to 77 K or even 4.2 K or below); 2) operation up to very high temperatures (e.g., to 200°C or even 300°C); 3) operation across very wide and/or cyclic temperature swings (e.g., -230°C +120°C night to day, as found on the lunar surface); 4) operation in a radiation environment (e.g., in space while orbiting the Earth); or 5) at worst case even with all four simultaneously. The unique bandgap-engineered features of silicon-germanium (SiGe) heterojunction bipolar transistors and the electronic circuits built from them offer a considerable potential for simultaneously coping with all four of these extreme environments, potentially with no process modifications, ultimately providing compelling advantages at the integrated circuit and system level across a wide class of envisioned commercial and defense applications. Here, we detail the nuances associated with using SiGe technology for extreme environment electronics, paying particular attention to recent developments in the field.

Note: Fully integrated time-to-amplitude converter in Si–Ge technology

Over the past years an always growing interest has arisen about the measurement technique of time-correlated single photon counting TCSPC), since it allows the analysis of extremely fast and weak light waveforms with a picoseconds resolution. Consequently, many applications exploiting TCSPC have been developed in several fields such as medicine and chemistry. Moreover, the development of multianode PMT and of single photon avalanche diode arrays led to the realization of acquisition systems with several parallel channels to employ the TCSPC technique in even more applications. Since TCSPC basically consists of the measurement of the arrival time of a photon, the most important part of an acquisition chain is the time measurement block, which must have high resolution and low differential nonlinearity, and in order to realize multidimensional systems, it has to be integrated to reduce both cost and area. In this paper we present a fully integrated time-to-amplitude converter, built in 0.35 μm Si-Ge technology, characterized by a good time resolution (60 ps), low differential nonlinearity (better than 3% peak to peak), high counting rate (16 MHz), low and constant power dissipation (40 mW), and low area occupation (1.38×1.28 mm(2)).

A direct-conversion WLAN transceiver baseband with DC offset compensation and carrier leakage reduction

A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11a/b/g standards is described. Several critical techniques for receiver DC offset compensation and transmitter carrier leakage rejection calibration are presented that enable the direct-conversion architecture to meet all WLAN specifications. The receiver baseband VGA provides 62 dB gain range with steps of 2 dB and a DC offset cancellation circuit is introduced to remove the offset from layout and self-mixing. The calibration loop achieves constant high-pass pole when gain changes; and a fast response time by programming the pole to 1 MHz during preamble and to 30 kHz during receiving data. The transmitter baseband employs an auto-calibration loop with on-chip AD and DA to suppress the carrier leakage, and AD can be powered down after calibration to save power consumption. The chip consumes 17.52 mA for RX baseband VGA and DCOC, and 8.3 mA for TX carrier leakage calibration (5.88 mA after calibration) from 2.85 V supply. Implemented in a 0.35 μm SiGe technology, they occupy 0.68 mm2 and 0.18 mm2 die size respectively.

Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement

Starting from the 90 nm technology node, process induced stress has played a key role in the design of high-performance devices. The emergence of source/drain silicon germanium (S/D SiGe) technique as the most important stressing mechanism for p-channel metal-oxide-semiconductor field-effect transistor devices has opened up various optimization possibilities at circuit and physical design stage. In this paper, we exploit the active area dependence of the performance improvement achievable using S/D SiGe technology for late stage engineering change order (ECO) timing optimization. An active area sizing aware cell-level delay model is derived which forms the basis of linear program based optimization of a design for achieving maximum performance or target performance under a timing budget. To control the magnitude of layout perturbation and ensure predictable timing improvement, a set of physical constraints for active area sizing is proposed. Further, an efficient minimum movement legalization algorithm is proposed to remove the overlaps caused by active area sizing of timing critical cells. Results on a wide variety of benchmarks show consistent reduction in the cycle time by up to 6.3%. Predictability of the performance improvement achievable as well as resultant minuscule layout changes make our technique very attractive for late stage ECO optimization and design closure.

A Subharmonic Receiver in SiGe Technology for 122$~$GHz Sensor Applications

The iterative design of an integrated subharmonic receiver for 120-127 GHz is presented. The receiver consists of a single-ended low-noise amplifier (LNA), a push-push voltage-controlled oscillator (VCO) with 1/32 divider, a polyphase filter, and a subharmonic mixer. The receiver is fabricated in SiGe:C BiCMOS technology with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fT</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 255 GHz/315 GHz. In the first design the differential down-conversion gain of the receiver is 25 dB at 127 GHz, and the corresponding noise figure (NF) is 11 dB. The 3 dB bandwidth reaches from 125 GHz to 129 GHz. The input 1 dB compression point is at - 40 dBm. The receiver draws 139 mA from a supply voltage of 3.3 V. A subsequent design demonstrates 31 dB differential gain at 122 GHz, and 11 dB NF. The 3 dB bandwidth is from 121 GHz to 124 GHz. The receiver has a NF of 8 dB for 3 GHz IF frequency due to integrated RF bandpass-filtering. It is realized by the lower NF of the LNA, and the LNA itself.

Generation of microwave chaotic oscillations in an integrated SiGe system

A self-oscillatory structure based on the SiGe technology is proposed for generation of dynamic chaos in the microwave range. A circuit dynamic model of this system taking into account the characteristics and constraints of applied active and passive elements and the circuit topology in a crystal is created. Dynamic regimes of the structure are studied; the existence of chaotic regimes is demonstrated, parameter domains corresponding to these regimes are determined. An SiGe crystal for a monolithic integrated chip realizing the proposed self-oscillatory structure according to the 0.25-μm technology is developed and manufactured. Chip operation regimes are studied, stable generation of ultrawideband chaotic oscillations in a range of 3–8 GHz is obtained.

A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology

The search for high speed, high bandwidth A/D converters is ongoing, and techniques to push the envelope are constantly being developed. In this paper an open loop, scalable, time-interleaved ADC architecture is presented, as well as a 60 GHz Colpitts oscillator. With the use of double-sampling, the timing skew requirements between channels is greatly relaxed, allowing sampling rates of up to 40 Gs/s at 4-bits of accuracy. This circuit is implemented using the IBM 8HP SiGe technology, with fT of 210 GHz. The performance of the 8HP ADC is validated by measurement. In addition, simulations with an experimental 8XP transistor model provided by IBM with a 350 GHz fT suggest that 30% more circuit speed is possible by just swapping the transistors.

Capacitive model for integrated PN varactors of cells with N+ buried layer

AbstractThis paper is devoted to analyzing varactors based on PN junction cells in order to obtain a capacitance model for radiofrequency (RF) applications. A cell is the minimum structure that can be considered a varactor, including all necessary layers and connections. Then, a specific capacitance for a RF integrated circuit is obtained overlapping all necessary cells horizontally and vertically. Our model estimates the total capacitance in a varactor, from both ports, considering all relevant internal contributions. Ten varactors based on the same cell have been designed and fabricated in 0.35 µm SiGe technology. These novel structures were also measured on‐wafer for frequencies ranging between 0.5 and 10 GHz, and voltages varying from 0 to −5 V. Our model predicts the capacitances in all cases with relative errors smaller than 10%. Copyright © 2010 John Wiley &amp; Sons, Ltd.

Wideband direct downconversion Gilbert mixer for 60 GHz applications

The design and the measurement results of a direct downconversion mixer for the 60 GHz ISM band are presented. Based on a Gilbert structure, the mixer is optimised for high bandwidth and designed in a 180 GHz SiGe technology. Without any buffer stages, the measured conversion gain is Gconv=−7 dB. The remarkably high IF bandwidth allows downconverting a continuous band of 15 GHz with flatness of ±1.4 dB and enables the design of ultra-high data rate transceivers.

High speeds in a single chip

This article reviews the development and breakthrough of SiGe technologies. SiGe HBTs with transit frequencies ft and maximum oscillation frequencies fmax above 300 GHz and monolithic integrated millimeter-wave circuits based on these HBTs have been developed by several groups. As this paper shows in the overview, the combination of active devices with passive planar structures, including antenna elements, allows single-chip realizations of complete millimeter-wave front-ends.

SIP antenna on 0.13 µm SiGe technology at 79 GHz for SRR automotive radar

This paper describes the analysis and the design of an integrated antenna on 0.13 µm SiGe BICMOS technology. A non-resonant dipole antenna integrated on SiGe is electromagnetically coupled to a radiating element reported on a printed circuit board (PCB) substrate. This integrated solution, also compatible with system in package (SIP) concept, provides significant improvements with respect to direct System On Chip (SoC) integration. The main objective of this SIP antenna lies on the optimization of integrated millimeter wave front-ends modules, considering the immediate antenna environment (especially the lossy substrate and technological dielectric/metallic levels), in order to achieve performances compatible with short range radar specifications at 79–81 GHz. One solution, using a RT/Rogers Duroid 6006 PCB (er = 6, thickness h = 127 µm), is presented, providing a 2.93 dBi gain, and 45% radiation efficiency antenna.

A 12-GHz High-Efficiency Tapered Traveling-Wave Power Amplifier With Novel Power Matched Cascode Gain Cells Using SiGe HBT Transistors

In this paper, we present the analysis, design, and implementation of an integrated power distributed amplifier (DA), fabricated in a low-cost 0.25-mum SiGe BiCMOS technology. The circuit consists of four novel inductively peaked cascode gain cells, which are capacitively coupled to the base line for power optimization and bandwidth enhancement. Due to the tapered collector line, no output termination resistor is required, which provides higher efficiency. Design tradeoffs for maximum bandwidth, gain, output power, and efficiency are discussed by means of analytical calculations and simulations. A gain of 11 dB with a gain flatness of plusmn1 dB has been measured over a frequency range from 1 to 12 GHz. 19.5-dBm output power is obtained at the 1-dB compression point (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> ) in the desired frequency range with an associated power-added efficiency of 22.1% and a maximum output third-order intercept point of 31.5 dBm. The power dissipation of the amplifier is 400 mW from a 5-V supply. On-chip biasing is implemented via low dropout voltage reference driven by a bandgap voltage source. To the authors' knowledge, this is the highest output power achieved by an HBT DA in SiGe technology in this frequency range. The chip size is 2.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Good agreement between simulation and measurement were achieved.

Evaluation of silicon-germanium (SiGe) bipolar technologies for use in an upgraded atlas detector

Silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technologies promise several advantages over CMOS for the front-end readout electronics for the ATLAS upgrade. We have evaluated the relative merits of the latest generations of IBM SiGe HBT BiCMOS technologies, the 8WL and 8HP platforms. These 130 nm SiGe technologies show promise to operate at lower power than do CMOS technologies and would provide a viable alternative for the silicon strip detector and liquid argon calorimeter upgrades, provided that the radiation tolerance studies at multiple gamma and neutron irradiation levels, included in this investigation, show them to be sufficiently radiation tolerant.

Concurrent dual-band SiGe HBT power amplifier for Wireless applications

This paper presents an investigation of a concurrent low-cost dual-band power amplifier (PA) fabricated in SiGe technology, able to simultaneously operate at two frequencies of 2.45 and 3.5-GHz, including an evaluation of its system level performance potentiality. Taking into account the technology novelty and the lack of device characterization and modeling, a hybrid (MIC) approach has been adopted both for a fast prototyping of the PA and for the evaluation of the device potentiality based on an extensive linear and nonlinear characterization. The comparison of PA performance in single-band or concurrent mode operation will be presented. In particular, the measured PA prototype shows an output power of 17.2 and 17-dBm at a 1-dB compression point, at 2.45 and 3.5-GHz, respectively, for CW single-mode operation, with a power added efficiency around 20%. System-level analysis predicts that, when the PA is operated under the 20-MHz Orthogonal Frequency-Division Multiplexing (OFDM) concurrent signals, the maximum output power levels to maintain the Error Vector Magnitude (EVM) within 5% are 11 and 3.5-dBm at 2.45 and 3.5-GHz, respectively. Moreover, new concepts and possible new system architectures for the development of the next generation of the multi-band transceiver front-end will be provided with an extensive system-level evaluation of the amplifier.

W-band double-balanced down-conversion mixer with Marchand baluns in silicon-germanium technology

Presented is a monolithic W-band (75–110 GHz) down-conversion mixer consisting of a double-balanced core, Marchand-type on-chip baluns at inputs, and a two-stage output buffer, fabricated in a 200 GHz fT SiGe technology. Including the loss for input baluns, this mixer exhibits conversion gains of 14.4±2.8 dB and single sideband (SSB) noise figures of less than 19.5 dB across the entire W-band, drawing 28 mA from a 3.3 V supply.