SiGe Technology Research Articles

Next generation integrated SiGe mm-wave circuits for automotive radar sensors

In this paper, radar transmitter circuits for next generation automotive radar sensors are presented. A 79 GHz radar transmitter with an output power of 14.5 dBm consuming only 165 mA (including frequency dividers) from a 3.3 V supply voltage clearly shows the advantage of using an improved SiGe technology with an fmax of 380 GHz. In addition, two radar transmitters for higher frequencies (around 150 GHz) based on frequency doubler circuits are showing the potential of SiGe technologies. The first transmitter achieves an output power of 3 dBm (single ended) at 144 GHz, whereas the second transmitters delivers a differential output power of 0 dBm at 150 GHz. Both transmitters achieve an ultra-wide tuning range of about 45 GHz.

A 79 GHz SiGe short-range radar sensor for automotive applications

The field of short- and mid-range radar sensors for automotive comfort and safety systems is a fast-growing market. The frequency regulation provides a new 76–81 GHz frequency band, which will be mandatory in the EU for ultra-wideband sensors from 2018. In the “radar-on-chip for cars” (RoCC) project funded by the German Ministry of Research (BMBF), a new technology was developed based on SiGe components with the objective to make the sensors affordable for all car platforms. This paper reports on the contribution of Continental A.D.C. GmbH to the joint “RoCC” project. The aim of the project was to exploit the cost-reduction potential of the SiGe technology by a further integration of the individual components and to show that the reliability and the functionality of the new sensors can meet the current requirements of the market. For this purpose, we evaluated the new eWLB package technology of Infineon. The Institute of Microwave Techniques of the University of Ulm supported us in designing a substrate integrated slotted waveguide antenna array. Demonstration sensors for short- and mid-range applications were built up and tested in the laboratory. To show the ability of the sensors to deal with real scenarios on the road, they were integrated into an experimental vehicle.

245-GHz LNA, Mixer, and Subharmonic Receiver in SiGe Technology

A four-stage common-base (CB) 245-GHz low-noise amplifier (LNA) and a fourth subharmonic 245-GHz transconductance mixer are presented. An integrated subharmonic receiver for sensing applications in the 245-GHz industrial-scientific-medical band is proposed. The receiver consists of a single-ended CB LNA, a fourth transconductance subharmonic mixer, a 60-GHz push-push voltage-controlled oscillator with a 1/32 divider, and an IF amplifier. It is fabricated in an SiGe: C BiCMOS technology with f T and fmax of 300 and 500 GHz, respectively. Its measured single-ended gain is 21 dB at 243 GHz with a tuning range of 12 GHz, and a noise figure of 33 dB. The input 1-dB compression point is -37 dBm . The receiver dissipates at 358 mW.

Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling

In this paper, the potential of Silicon-Germanium (SiGe) technology for VLSI logic applications is investigated from a circuit perspective for the first time. The study is based on experimental measurements on 45-nm SiGe pMOSFETs with a high- κ/metal gate stack, as well as on 45-nm Si pMOSFETs with identical gate stack for comparison. In the reference SiGe technology, an innovative technological solution is adopted that limits the SiGe material only to the channel region. The resulting SiGe device merges the higher speed of the Ge technology with the lower leakage of the Si technology. Appropriate circuit- and system-level metrics are introduced to identify the advantages offered by SiGe technology in VLSI circuits. Analysis is performed in the context of next-generation VLSI circuits that fully exploit circuit- and system-level techniques to improve the energy efficiency through aggressive voltage scaling, other than low-leakage techniques. Analysis shows that the SiGe technology has more efficient leakage-delay and dynamic energy-delay trade-offs at nominal supply, compared to Si technology. Moreover, it is shown that the traditional analysis performed at nominal supply actually underestimates the benefits of SiGe pMOSFETs, since the speed advantage of SiGe VLSI circuits is further emphasized at low voltages. This demonstrates that SiGe VLSI circuits benefit from aggressive voltage scaling significantly more than Si circuits, thereby making SiGe devices a very promising alternative to Si transistors in next-generation VLSI systems.

Subharmonic 220- and 320-GHz SiGe HBT Receiver Front-Ends

Monolithically integrated 220- and 320-GHz receiver front-ends manufactured in an engineering version of anfT/fmax=280/435-GHz SiGe technology are presented. Subharmonic mixing is provided by a Gilbert cell with stacked switching quads fed by quadrature 110/160-GHz local oscillator (LO) signals. The 220-GHz version of the front-end is equipped with an integrated LNA with a measured 15-dB gain and 28-GHz bandwidth. This front-end yields a conversion gain of 16 dB, an 18-dB single-sideband (SSB) noise figure (NF), and a 30-GHz bandwidth when pumped with a 0-dBm 110-GHz LO signal. The 320-GHz version of the front-end omits the low-noise amplifier and features an integrated × 9 LO multiplier chain to facilitate operation and characterization. A conversion gain of -14 dB and a 36-dB SSB NF is obtained over the 313-to-328-GHz frequency range. The presented circuits demonstrate that a fully integrated receiver front-end can be implemented up to submillimeter-wave frequencies in an SiGe HBT technology.

Bandwidth-Related Optimization in High-Speed Frequency Dividers using SiGe Technology

In this paper, the trade-off related to bandwidth of high-speed common-mode logic frequency divider is analyzed in detail. A method to optimize the operating frequency, band-width as well as power consumption is proposed. This method is based on bipolar device characteristics, whereby a negative resistance model can be used to estimate the optimal normalized upper frequency and lower frequency of frequency dividers under different conditions, which is conventionally ignored in literatures. This method provides a simple but efficient procedure in designing high performance frequency dividers for different applications. To verify the proposed method, a static divide-by-2 at millimeter wave ranges is implemented in 180 nm SiGe technology. Measurement results of the divider demonstrate significant improvement in the figure of merit as compared with literatures.

Four Channel, 40 ps Resolution, Fully Integrated Time-to-Amplitude Converter for Time-Resolved Photon Counting

Recently, a growing interest has arisen about the time-correlated single photon counting (TCSPC) technique, that allows the analysis of fast and weak light waveforms with a time resolution in the picosecond order. Since TCSPC basically consists of the measurement of the arrival time of a photon, a high resolution and high linearity time measurement block is of the utmost importance; moreover, the use of multianode Photo Multiplier Tube and of single photon avalanche diode arrays led to the development of multichannel acquisition systems, where the time measurement block has to be integrated to reduce both cost and area. We have designed and fabricated a four channel fully integrated time-to-amplitude converter (TAC), built in 0.35 μm Si-Ge technology, characterized by an excellent time resolution (less than 50 ps full width half maximum), low differential nonlinearity (better than 0.02 LSB peak-peak and 0.0003 LSB rms), high counting rate (16 MHz), low and constant power dissipation (50 mW) and low area occupation (2.58 × 1.28 mm2 ). Moreover, the very low crosstalk ( -115 dB) between channels, together with low power and low area makes the converter suitable for large scale multi-channel acquisition chains.

A Narrow-band 8.7 GHz SiGe HBT LNA with a Passive Frequency Selective Feedback

AbstractThis paper presents a low noise amplifier (LNA) with differential output using a passive frequency selective feedback. The introduced feedback stabilizes the amplifier at lower frequencies and improves the gain in the desired frequency band. The LNA consists of two stages. Additionally, a buffer at the output is added for measurements. The amplifier was implemented in a 0.35 μm SiGe technology. For measurements the LNA was bonded to a substrate. A peak gain of 28.1 dB and a minimum noise figure of 2.2 dB at a supply voltage of 3 V were achieved.

Homogeneity of Ge-rich nanostructures as characterized by chemical etching and transmission electron microscopy

The extension of SiGe technology towards new electronic and optoelectronic applications on the Si platform requires that Ge-rich nanostructures be obtained in a well-controlled manner. Ge deposition on Si substrates usually creates SiGe nanostructures with relatively low and inhomogeneous Ge content. We have realized SiGe nanostructures with a very high (up to 90%) Ge content. Using substrate patterning, a regular array of nanostructures is obtained. We report that electron microscopy reveals an abrupt change in Ge content of about 20% between the filled pit and the island, which has not been observed in other Ge island systems. Dislocations are mainly found within the filled pit and only rarely in the island. Selective chemical etching and electron energy-loss spectroscopy reveal that the island itself is homogeneous. These Ge-rich islands are possible candidates for electronic applications requiring locally induced stress, and optoelectronic applications which exploit the Ge-like band structure of Ge-rich SiGe.

Wideband (500 MHz) 16 bit dynamic range current mode PreAmplifier for the CTA cameras (PACTA)

A wideband current mode preamplifier with 16 bits dynamic range (DR) is presented. It has been designed for the cameras of the Cherenkov Telescope Array (CTA). A novel current division scheme at the very front end part of the circuit splits the input current into two scaled currents which are connected to independent current mirrors. The mirror of the high gain path comprises a saturation control circuit for accurate current division. Measurement results of an ASIC designed in Austriamicrosystems 0.35 μm SiGe technology are presented: 500 MHz BW, 16 bits DR, 10 pA/sqrt(Hz) input referred noise current and relative linearity error below 3%.

KLauS – A charge readout and fast discrimination chip for silicon photomultipliers

KLauS is an application specific integrated circuit (ASIC) for the readout of silicon photomultipliers. The chip has been designed for the application in the analog hadronic calorimeter developed by the CALICE collaboration for the next linear collider experiment . To address the severe power constraints introduced by the highly granular design of the calorimeter, the chip has been designed for low power consumption while maintaining the high dynamic range and timing precision required by the experiment. In addition, a power gating scheme has been implemented to further decrease the average power consumption. For a duty cycle of 1 % a value of 25 μW per channel is achieved without affecting the readout capabilities of the chip. The chip has been designed in the 0.35 μm SiGe technology and provides a low power readout channel for SiPMs with low gain for the input stage of the existing readout chip SPIROC. The analog channel of KLauS will be implemented in a future version of the SPIROC chip.

EASIROC, an Easy & Versatile ReadOut Device for SiPM

Abstract EASIROC, standing for Extended Analogue Si-pm Integrated ReadOut Chip is a 32 channels fully analogue front end ASIC dedicated to readout SiPM detectors. This low power and highly versatile ASIC was developed from the chip SPIROC[1] which has been designed for the Analogue Hadronic Calorimeter foreseen at the International Linear Collider. EASIROC integrates a 4.5 V range 8-bit DAC per channel for individual SIPM gain adjustment. A multiplexed charge measurement from 160 fC up to 320 pC is available thanks to 2 analogue outputs. These charge paths are made of 2 variable gain preamplifiers followed by 2 tuneable shapers and a track and hold. A trigger path integrates a fast shaper followed by a discriminator the threshold of which is set by an integrated 10-bit DAC. These 32 trigger outputs can be used for timing measurements. The power consumption is lower than 5 mW/channel and unused features can be powered OFF to decrease the power. The chip has been designed in AMS 0.35 μm SiGe technology and 4000 dies have been produced in 2010. Its versatility allows its use in many photo detector experiments and is already used for PEBS, MuRAY, J-PARC and medical imaging.

A Programmable Compensation Circuit for System-on-Chip Application

This paper presents a new programmable compensation circuit (PCC) for a System-on-Chip (SoC). The PCC is integrated with O.18-J.1m BiCMOS SiGe technology. It consists of RF Design-for-Testability (DFT) circuit, Resistor Array Bank (RAB) and digital signal processor (DSP). To verify performance of the PCC we built a 5-GHz low noise amplifier (LNA) with an on-chip RAB using the same technology. Proposed circuit helps it to provide DC output voltages, hence, making the RF system chain automatic. It automatically adjusts performance of an LNA with the processor in the SoC when it goes out of the normal range of operation. The PCC also compensates abnormal operation due to the unusual PVT (Process, Voltage and Thermal) variations in RF circuits.

(Invited) Radiation Hardness of SiGe and Ge-Based CMOS Technologies

To cope with the devices requirements imposed with the ITRS roadmap, several technique are implemented to boost up the drive current. Two possible approaches are the introduction of SiGe channels and the use of Ge-based devices. This paper reviews the radiation hardness of both CMOS technologies, based on an experimental study of state-of-the-art devices, for potential use in space applications.

An ASIC design for LHAASO

The ASIC is widely used in the field of high energy physics. Astroparticle experiments benefit from high integration, small size and low power consumption. In this paper an analog chip named ARCHGARD (Analog Readout Chip for High energy Gamma Ray Detector) for high energy physics experiment is introduced. ARCHGARD is a readout chip, in chartered 0.35 μm SiGe technology, for photomultipliers (PMT) array readout. The chip is designed for the Large High Altitude Air Shower Observatory (LHAASO) project. The ASIC integrates 16 independent and auto-triggered channels with variable gain and variable shaping time. It provides analog output for charge measurement, which is performed from 1 up to 3000 photo-electrons (p.e.). The integral nonlinearity of the whole input range is less than 1% and the equivalent input noise is less than 1/10 p.e. Each channel has a trigger output for time measurement.

A 6-bit Fully Binary Digital-to-Analog Converter in 0.25-$\mu{\hbox {m}}$ SiGe BiCMOS for Optical Communications

This paper presents an approach to implement a high-speed binary weighted digital-to-analog converter (DAC). A different current switching mechanism is proposed that improves the dynamic performance of binary weighted DACs. Circuit simulation shows an improvement of the rise (fall) time mismatch by a factor of 2 over the conventional structure. It is shown that in a conventional high-speed binary DAC implemented with differential pairs, the spurious-free dynamic range (SFDR) can be degraded by nearly 6 dB due to the different rise (fall) times of the current switches. Using the proposed current switches, a fully binary weighted DAC with nominal resolution of 6 bit has been fabricated in 0.25-μm SiGe technology. The measured SFDR is higher than 30.1 dBc up to 5.9-GHz input signal with a 13.4-GHz clock. The DAC can provide 1.1-V peak-to-peak differential output swing over 50 Ω while dissipating 1050 mW. Full-scale 20%-80% fall time and 2% settling time are measured below 18 and 45 ps, respectively.

A 122-GHz SiGe-Based Signal-Generation Chip Employing a Fundamental-Wave Oscillator With Capacitive Feedback Frequency-Enhancement

This paper presents a highly integrated and fully balanced signal generation block comprising a fundamental-wave voltage-controlled oscillator (VCO), an output buffer, and a configurable frequency divider stage (prescaler). The VCO introduces a negative resistance structure in conjunction with capacitive cross-coupling. This compound structure allows fundamental oscillation to be sustained at high frequencies while providing wide tuning ranges. The capabilities of the capacitive feedback were analyzed using a linear transistor model, and boundary conditions, which support the early design phase, were derived. The chip was fabricated in a SiGe technology with 300-GHz <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> HBTs. The output frequency of the monolithic microwave integrated circuit is centered at 122 GHz and provides a tuning range of 16 GHz at an average single-sideband phase noise of -95 dBc/Hz at 1 MHz offset frequency. Possible applications include ISM applications at 122 GHz and short-range radar systems with wide tuning ranges.

60 GHz wide tuning range SiGe bipolar voltage controlled oscillator for high definition multimedia interface and wireless docking applications

A wide tuning range voltage controlled oscillator (VCO) with novel architecture is proposed in this work. The entire circuit consists of a VCO core, a summing circuit, a single-ended to differential (STD) converter and a buffer amplifier. The VCO core oscillates at half the desired frequency and the second harmonic of the VCO core is extracted by the summing circuit, which is then converted to a differential pair by the STD. The entire VCO circuit operates from 58.85 to 70.85 GHz with 20% frequency tuning range. The measured VCO gain is less than 1.6 GHz/V. The measured phase noise at 3 MHz offset is less than -78 dBc/Hz across the entire tuning range. The differential phase error of the output signals is measured by down converting the VCO output signals to low gigahertz frequency using an on-chip mixer. The measured differential phase error is less than 8°. The VCO circuit, which is constructed using 0.35 μm SiGe technology, occupies 770 × 550 μm 2 die area and consumes 62 mA under 3.5 V supply.

Physical layer design, link budget analysis, and digital baseband implementation for 60 GHz short-range applications

The large bandwidth of the 60 GHz frequency band enables wireless short-range applications with data rates of several Gbit/s. The German project EASY-A has focused on early prototype implementations for selected applications, although no generally accepted 60 GHz standard has been available at the time. The implementations are based on application-oriented physical layer designs and link-budget investigations that account for the scenario-specific channel characteristics and for different integration technologies. This paper discusses the results of these investigations and details the hardware implementation of the digital baseband processing that relies on considerable parallelization. The link-budget results show that SiGe technology allows for 1 Gbit/s at a range of 3.5 m in non-line-of-sight environments, while up to 10 Gbit/s are feasible at more than 1 m in case of strong line of sight.

High-performance 60 GHz MMICs for wireless digital communication in 100 nm mHEMT technology

Wireless data communication is pushing towards 60 GHz and will most likely be served by SiGe and Complementary Metal Oxide Semiconductor (CMOS) technologies in the consumer market. Nevertheless, some applications are imposing superior performance requirements on the analog frontend, and employing III-V compound semiconductors can provide significant advantages with respect to transmitter power and noise figure. In this paper, we present essential building blocks and a novel single-chip low complexity transceiver Monolithic Microwave Integrated Circuit (MMIC) with integrated antenna switches for 60 GHz communication, fabricated in a 100 nm metamorphic high electron mobility transistor (mHEMT) technology. This technology features a measured noise figure of &lt;2.5 dB in low-noise amplifiers at 60 GHz and the realized medium power amplifiers achieve more than 20 dBm saturated output power. Integrated antenna switches with an insertion loss of less than 1.5 dB enable the integration of the transmit and the receive stages on a single chip. A single-chip transceiver with external subharmonic Local Oscillator (LO) supply for its I/Q down- and up-converter achieves a linear conversion gain in both, the Transmit (Tx) and the Receive (Rx) paths, of more than 10 dB.