Strain-relaxed SiGe Buffer Research Articles

Dislocation structures and strain-relaxation in SiGe buffer layers on Si (0 0 1) substrates with an ultra-thin Ge interlayer

Strained Si channel layers grown on relaxed SiGe layers have become attractive for the application to high-speed Si-based devices. Several methods have been developed in order to realize high-quality strain-relaxed SiGe buffer layers which induce the strain in the channel. In this work, we have used an ultra-thin Ge interlayer (with a thickness in the range of 0.5–5.0 nm) formed at the SiGe/Si(0 0 1) substrate interface to obtain thin strain-relaxed SiGe buffer layers. By using this method, we have not only controlled the residual strain of SiGe buffer layers but also realized thin strain-relaxed SiGe buffer layers with smooth surfaces. Moreover, we have confirmed the changes of dislocation structures as the thickness of Ge interlayer increased. This structural change of dislocations leads to the effective strain-relaxation along the direction parallel to the interface.

Surface Planarization of Strain-Relaxed SiGe Buffer Layers by CMP and Post Cleaning

Surface planarization of strain-relaxed SiGe buffer layers by chemical mechanical polishing (CMP), particularly the influence of a post-CMP cleaning process which is indispensable after CMP, on the surface morphology of SiGe buffer layers was investigated. It was found that the cleaning tended to enhance the surface roughness due to the etching effect that increased with increasing cleaning temperature. The etching effect was suppressed by optimizing cleaning reagents, and the ultrasmooth surfaces of SiGe buffer layers with Ge contents of 30 to 70% were obtained, irrespective to growth methods. The root mean square roughness reached 0.4 to 0.6 nm, which was the lowest value that was ever obtained. © 2003 The Electrochemical Society. All rights reserved.

Mobility enhancement in strained Si modulation-doped structures by chemical mechanical polishing

The strained Si modulation-doped (MOD) structure formed on the strain-relaxed SiGe buffer layer planarized by chemical mechanical polishing (CMP) was found to show significant mobility enhancement. The enhancement reaches a factor of 6 at low temperatures. The backgate dependence as well as temperature dependence of the transport properties of the MOD structure were investigated, and it was suggested that CMP drastically reduced the roughness scattering and increased the mobility of two-dimensional electron gas in the strained Si.

Planarization of SiGe virtual substrates by CMP and its application to strained Si modulation-doped structures

Ultrasmooth strain-relaxed SiGe buffer layer with rms roughness of 0.4 nm was obtained by chemical mechanical polishing (CMP). The strained Si modulation-doped structure grown on the planarized buffer layer showed mobility enhancement by a factor of 6 at low temperatures. Thermal stability of the strained Si layer was also found to be improved by CMP, which may come from the reduction of dislocation nucleation sites related to the surface undulation.

Micro-Raman investigations of the degree of relaxation in thin SiGe buffer layers with high Ge content

Virtual substrates with high Ge content x of 0.25<x<0.5 for metal oxide semiconductor field effect transistor (nMOSFET) structures are grown by molecular beam epitaxy (MBE). Thin strain-relaxed SiGe buffers are of special importance for this application, therefore, sub-100 nm layer growth procedures have been developed. Micro-Raman spectroscopy has been extensively employed for measurements of Ge content and the degree of relaxation (r) in our virtual substrates. Two growth stages – a very low temperature (VLT) stage and overgrowth at 550 °C (OT stage) were used to provide the high relaxation in thin SiGe layers. Implementation of this process under careful temperature control within 50 °C during the VLT growth stage allows us to regulate precisely the degree of relaxation. The role of low temperatures and of Sb surfactants during the VLT growth stage for process-window widening is studied. The Sb pre-buildup is found to increase the degree of relaxation in a higher temperature range during the VLT stage. Optimum processing conditions are determined and high uniformity of composition and residual-strain distribution on virtual substrate wafers are demonstrated.

Thin SiGe buffers with high Ge content for n-MOSFETs

Virtual substrates for n-MOSFET structures are grown by MBE with high Ge content of 0.25< x<0.5. Since thin strain relaxed SiGe buffers are of a special importance for this application sub-100 nm layer growth procedure is developed. Extremely low temperatures and Sb surfactants are implemented during the first growth stage of the SiGe buffers. The role of these factors in crystal structure formation is in situ monitored by reflectivity measurements. ‘Process windows’ for both methods are determined. The Sb pre-build up is found to increase the degree of relaxation and to contribute to the surface smoothness. Implementation of this method under precise temperature variation within 50 °C, allows us to regulate degrees of relaxation between values of 2 and 99%. SIMS, X-ray diffraction (XRD) and μ-Raman are employed for measurements of Ge content, composition profiles and degree of relaxation. Surface morphology of the layers is characterised by atomic force microscopy.

Surface smoothing of SiGe strain-relaxed buffer layers by chemical mechanical polishing

We flattened the rough surface of the strain-relaxed Si 0.7Ge 0.3 buffer layers by chemical mechanical polishing technique and successfully obtained the ultra-smooth surface whose root mean square roughness was less than 1 nm. The regrowth of Si 0.7Ge 0.3 films on the polished Si 0.7Ge 0.3 buffer layer was found to keep its surface roughness less than 1 nm, and efficient photoluminescence with narrow line width was observed from quantum wells grown on the polished buffer layer. This indicates high crystalline quality of the regrown layer with smooth interfaces, which makes it possible to fabricate high-performance SiGe devices with low surface roughness scattering.

Reduction of threading dislocation density in SiGe layers on Si (001) using a two-step strain–relaxation procedure

A method to obtain high-quality strain–relaxed SiGe buffer layers on Si(001) substrates is presented. In this method, the strain relaxation of the SiGe layer is performed using a two-step procedure. Firstly, a low-temperature-grown SiGe layer, whose surface is covered by a thin Si cap layer, is thermally annealed. At this stage, the strain is incompletely relaxed and an atomically flat surface can be realized. Then, a second SiGe layer is grown on the first layer to achieve further strain relaxation. Transmission electron microscopy has clearly revealed that dislocations are dispersively introduced into the first SiGe/Si substrate interface and thus no pile up of dislocations occurs. The formation of a periodic undulation on the growth surface of the second SiGe layer is the key to inducing a drastic reduction in the threading dislocation density.

Fully relaxed Si0.7Ge0.3 buffers grown on patterned silicon substrates for hetero-CMOS transistors

For a successful fabrication of hetero-CMOS transistors the compatibility of the epitaxial growth of the heterostructures with the standard CMOS process is an important factor. A very promising integration approach utilizes the realization of heterostructures in a limited area, so-called differential epitaxy. In this paper, we report on new results of fully strain-relaxed SiGe buffers (SRB) with a thickness of about 750 nm, i.e. on the order of the thickness of the field oxide in the standard CMOS technology. The SiGe SRB layers completed by active device layer stacks were grown by several growth concepts, linearly and step-graded buffers and in comparison a method using a low-temperature epitaxial Si (LTE-Si) starting layer. The influence of lateral dimensions and of the different growth concepts on the surface morphology, relaxation and defect density has been investigated. Differential interference contrast (DIC) micrographs and atomic force measurements (AFM) were applied to characterize the surface topography. The relaxation measurements in the patterned areas were performed using micro-Raman spectroscopy. The analysis of the dislocations was carried out by transmission electron microscopy (TEM). Two main results should be emphasized: Full relaxation (also in the small window) was only achieved for the SiGe buffer with 50-nm LTE-Si and TEM images show different dislocation structures for a graded buffer and the buffer with 50-nm LTE-Si.

Modulation doping in the Si/SiGe heterosystem

A review is given of the most recent development in the field of modulation doping in the Si/SiGe heterosystem. Main topics are the successful implementation of high-quality, strain-relaxed SiGe buffers, the realization of n-type quantum well structures with unprecedentedly high electron mobilities, magnetotransport investigations of such structures, and their exploitation for test devices with very high transconductance values.

Two-dimensional electron gas properties of symmetrically strained Si/Si1−xGex quantum well structures

Abstract n-type modulation-doped Si/Si 0.5 Ge 0.5 strained layer multiple quantum well structures have been grown on (100)Si substrates by molecular beam epitaxy. The concept of strain symmetrization has been applied by inserting a strain-relaxed SiGe buffer layer. The samples have been investigated by Hall measurements supplemented by Shubnikov-de Haas and Rutherfored backscattering analysis. We present mobility results on the two-dimensional electron gas in the silicon wells as a function of electron concentration, quantum well width, and spacer thickness. The influence of the sample parameters on the electron mobility is discussed. With an electron sheet concentration of 2.4×10 12 cm −2 per well, a well width of 10 nm, and a spacer thickness of 10 nm a Hall mobility at room temperature of 1280 cm 2 (V s) -1 has been achieved.