Fully relaxed Si0.7Ge0.3 buffers grown on patterned silicon substrates for hetero-CMOS transistors

Abstract

For a successful fabrication of hetero-CMOS transistors the compatibility of the epitaxial growth of the heterostructures with the standard CMOS process is an important factor. A very promising integration approach utilizes the realization of heterostructures in a limited area, so-called differential epitaxy. In this paper, we report on new results of fully strain-relaxed SiGe buffers (SRB) with a thickness of about 750 nm, i.e. on the order of the thickness of the field oxide in the standard CMOS technology. The SiGe SRB layers completed by active device layer stacks were grown by several growth concepts, linearly and step-graded buffers and in comparison a method using a low-temperature epitaxial Si (LTE-Si) starting layer. The influence of lateral dimensions and of the different growth concepts on the surface morphology, relaxation and defect density has been investigated. Differential interference contrast (DIC) micrographs and atomic force measurements (AFM) were applied to characterize the surface topography. The relaxation measurements in the patterned areas were performed using micro-Raman spectroscopy. The analysis of the dislocations was carried out by transmission electron microscopy (TEM). Two main results should be emphasized: Full relaxation (also in the small window) was only achieved for the SiGe buffer with 50-nm LTE-Si and TEM images show different dislocation structures for a graded buffer and the buffer with 50-nm LTE-Si.