SiGe Selective Epitaxial Growth Research Articles

Investigation on the formation technique of SiGe Fin for the high mobility channel FinFET device

In this work, SiGe Fin formation technique using shallow trench isolation (STI) first or STI last strategy for the high mobility channel FinFET device is systematically investigated. A 20 nm width and 35 nm height high crystalline quality of the Si0.7Ge0.3 Fin formation for STI first scheme is demonstrated by utilizing a new developed Si Fin etching, Si Fin recess and SiGe selective epitaxial growth process. For the STI last strategy, a novel chemical mechanical planarization (CMP) treated three-layer SiGe strain relaxed buffer (SRB) is successfully fabricated and a 50 nm high crystal quality and atomically smooth surface Si0.5Ge0.5 layer on this SRB is attained. Moreover, a spike annealing is employed to avoid the Si0.5Ge0.5 Fin oxidation during STI densification with an acceptable STI etching rate. However, both a spike annealing and a lower temperature of traditional furnace at 850 °C or 750 °C suffer micro-trench issue during the Fin reveal process. Therefore, a new developed process, named as STI recess first, is developed to resolve both thermal instability and micro-trench issue at the same time. A minor Si0.5Ge0.5 Fin loss with a sharp Si0.7Ge0.3 SRB/Si0.5Ge0.5 interfaces for STI last scheme is realized by utilizing this new developed STI recess first process.

Sige Selective Epitaxial Growth Process for 22 Nm Node CMOS and Beyond

As CMOS technology downscales into 22nm and beyond nodes, strain engineering technologies are widely used to improve the short channel effect and enhance MOS mobility to make high performance devices. During these technology developments, SiGe selective epitaxial growth has been used as stressor material in source and drain (S/D) region to induce uniaxial strain in channel region [1].In order to further enhance the MOS channel mobility, the recess shape has to be designed to create maximum strain from the grown SiGe layers. To achieve this goal the etch step has been modified to elaborate a sigma (∑) shape recess and a high Ge content film is deposited in S/D regions [2]. Then SiGe epitaxy process becomes sensitive to surface quality of the recess where a careful etching and in- and ex-situ cleaning are demanded.In this study, selective Si1-xGex growth (0.25≤x≤0.35) with boron concentration of 1-3×1020 cm-3for 22nm node CMOS process has been investigated (see Fig.1). The selectivity issue has examined/tuned around the gate region where both nitride and oxide layers were presented and the thermal budget was decreased to 800 °C to preserve the sigma shape in the S/D regions (see Fig.2).The structures contained two Si1-xGex layers; where the recess was filled first with Si0.65Ge0.35 and then a cap Si0.75Ge0.25layer to elevate the S/D regions. The purpose for having the elevated SiGe cap layer was to avoid strain relaxation in the SiGe bottom layer during the Ni-silicidation process.The Ge content in epi-layers on the chips was measured directly by rocking curves (RCs) using high-resolution x-ray diffraction (HRXRD). RC were done at (113) reflection where the incident beam is as low as 2.6° and a large area of sample containing an enormous of number of transistors could be covered by x-ray beam. These RCs were simulated by the Takagi-Taupin equations and compared to the experimental curves in order to obtain the high precision data analysis[3]. In these measurements, the boron concentration was estimated by the strain compensation in SiGe layers. The shift of B-doped SiGe peak was compared to the intrinsic ones and interpreted into the substitutional dopant concentration. In these SiGe layers, the B dopant concentration was quite high and the strain compensation could easily be measured.Cross-section images where provided by high-resolution scanning electron microscopy (HRSEM) and transmission electron microscopy (HRTEM) to measure the layer thickness, epi-quality, and integrity of the whole transistor structures. In the latter analysis, energy dispersive spectroscopy (EDS) technique was also employed to measure the Ge profile in parallel and perpendicular directions in the S/D regions of the transistors.

Low temperature boron and phosphorous doped SiGe for recessed and raised sources and drains

We have first of all studied the growth kinetics of boron and phosphorous doped, 20–30 nm thick Si 0.65Ge 0.35 layers, the aim being their integration in recessed and raised sources and drains. Those layers have been grown at low pressure (20 Torr) and low temperature (650 °C) with a heavily chlorinated chemistry (in order to be selective versus SiO 2 (isolation) and Si 3N 4 (sidewall spacers)). We have quantified the impact of the diborane and phosphine flow on (i) the SiGe crystalline quality and strain state, (ii) the amount of boron or phosphorous atoms incorporated in it and (iii) the SiGe:B or SiGe:P growth kinetics. As the diborane flow increases, the SiGe:B growth rate definitely increases, while the real Ge concentration (from Time-Of-Flight Secondary Ions Mass Spectrometry) is more or less steady. B atoms, being much smaller than Si or Ge, partially compensate the compressive strain in the SiGe:B layers, leading to a decrease in the apparent Ge concentration (from X-ray diffraction). Opposite trends are observed for SiGe:P. There is indeed a definite decrease in the SiGe:P growth rate together with a definite increase in both the apparent and real Ge concentration as the phosphine flow increases. The Boron atomic concentration increases linearly with the diborane flow, with however a practical limit around 3.5×10 20 cm −3 in order to stay monocrystalline. Meanwhile, the phosphorous atomic concentration saturates quite rapidly at values close to 8–9×10 19 cm −3 as the phosphine flow increases (most likely due to surface segregation). In the second part we have highlighted some of the difficulties encountered when trying to selectively grow intrinsic SiGe raised S/Ds at 650 °C on patterned, extra-thin Silicon-On-Insulator wafers and some of the solutions identified in order to obtain 2D thick films. Amongst those, we can mention the 750 °C deposition of a thin Si buffer or the in-situ high HCl partial pressure etch at 650 °C of a few nm of Si prior to SiGe Selective Epitaxial Growth (SEG), the drastic reduction of the incoming HCl flow during SiGe SEG, etc.

Kinetic Model of SiGe Selective Epitaxial Growth using RPCVD Technique

Recently, selective epitaxial growth (SEG) of B-doped SiGe layers has been used in recessed source/drain (S/D) of p-channel metal-oxide-semiconductor field-effect transistor. The uniaxial induced strain enhances the carrier mobility in the channel. In this work, a detailed model for SEG of SiGe has been developed to predict the growth rate and Ge content of layers in dichlorosilane (DCS)-based epitaxy using a reduced-pressure chemical vapor deposition (RPCVD) reactor. The model considers each gas precursor contributions from the gas-phase and the surface. The gas flow and temperature distribution were simulated in the chemical vapor deposition reactor, and the results were exerted as input parameters for Maxwell energy distribution. The diffusion of molecules from the gas boundaries was calculated by Fick’s law, and the Langmuir isotherm theory (in nonequilibrium case) was applied to analyze the surface. The pattern dependency of the selective growth was also modeled through an interaction theory between different subdivisions of the chips. Overall, a good agreement between the kinetic model and the experimental data was obtained.

Kinetic Model of SiGe Selective Epitaxial Growth Using RPCVD Technique

Recently, selective epitaxial growth (SEG) of B-doped SiGe layers has been used in recessed source/drain (S/D) of pMOSFETs. The uniaxial induced strain enhances the carrier mobility in the channel. In this work, a detailed model for SEG of SiGe has been developed to predict the growth rate and Ge content of layers in dichlorosilane(DCS)-based epitaxy using a reduced-pressure CVD reactor. The model considers each gas precursor contributions from the gas-phase and the surface. The gas flow and temperature distribution were simulated in the CVD reactor and the results were exerted as input parameters for Maxwell energy distribution. The diffusion of molecules from the gas boundaries was calculated by Fick's law and Langmuir isotherm theory (in non-equilibrium case) was applied to analyze the surface. The pattern dependency of the selective growth was also modeled through an interaction theory between different subdivisions of the chips. Overall, a good agreement between the kinetic model and the experimental data were obtained.

SiGe nanostructure fabrication through selective epitaxial growth using self-assembled nanotemplates

Ordered SiGe nanostructures including nanodots (NDs) and nanowires (NWs) were fabricated via selective epitaxial growth (SEG) of SiGe using ultrahigh vacuum chemical vapour deposition (UHV-CVD) on Si openings fabricated using self-assembled nanotemplates of anodic anluminum oxide (AAO) and diblock copolymer (DBC) of polystyrene-block-polymethylmethacrylate (PS-b-PMMA), exhibiting hexagonally arranged nanoholes. SiGe SEG was processed through repeating the unit cycle composed of two separated steps of SiGe growth using disilane (Si2H6) and Germane (GeH4) and chlorine (Cl2 exposure. Cl2 was used to improve the selectivity of SiGe SEG between the Si openings and the oxide area. Ordered SiGe NDs and NWs were fabricated through SiGe SEG of 20 cycles and 400 cycles on AAO/Si, respectively. In addition, ordered SiGe NDs were obtained via SiGe SEG of 20 cycles on SiO2 template, fabricated through pattern transfer of nanoholes of PS-b-PMMA to SiO2/Si. SiGe nanostructure fabrication using both AAO and PS-b-PMMA showed good replication of the nanohole size of the nanotemplates.An erratum to this article was added by the author on 18 May 2010. The text of the erratum is appended to the PDF.

Multi-gate devices for the 32 nm technology node and beyond: Challenges for Selective Epitaxial Growth

This work will focus on the use of Selective Epitaxial Growth (SEG) of Si and SiGe in multi-gate devices. We will demonstrate the necessity of using SEG in the processing of these narrow fin devices. Reductions of the source/drain resistance and Gate Induced Drain Leakage (GIDL) are the main advantages of using SEG. Although the use of SiGe SEG has little impact as mobility booster in narrow fin pMOS devices, it provides a significant reduction in contact resistance.

Atmospheric In situ Arsenic-Doped SiGe Selective Epitaxial Growth for Raised-Extension N-type Metal–Oxide–Semiconductor Field-Effect Transistor

We have investigated the AsH3 and GeH4 flow rate dependences of As concentration and growth rate for atmospheric in situ As-doped SiGe selective epitaxial growth. A high As concentration of 3.2×1019 atoms/cm3 and a high growth rate of 13 nm/min were achieved for Si0.79Ge0.21 selective epitaxial growth. The good selectivity was confirmed, and the epitaxial film showed high crystalline quality, a smooth surface and an abrupt change in the dopant profile at the interface. These results were interpreted in terms of the suppression of As surface segregation and the enhancement of As diffusion due to Ge incorporation in Si growth.

Selective Epitaxy of Si/SiGe to Improve pMOS Devices by Recessed Source/Drain and/or Buried SiGe Channels

Selective Epitaxial Growth of SiGe and/or Si-cap/SiGe heterostructures offer an elegant way to improve pMOS device performance. This paper discusses some important challenges and characteristics of the corresponding epi process. Loading effects are strongly reduced by choosing the growth conditions away from the mass transport regime, i.e. by reducing the growth pressure and/or increasing the gas velocity. Anomalous SiGe thickening at convex corners of recessed areas and the impact of the underlying SiGe on the growth behavior during Si- capping are discussed as well. The limits of the chemical and thermal budgets during pre-epi treatments as defined by the device concepts require some process optimization but are not a show stopper.

Selective epitaxial growth of SiGe for strained Si transistors

A selective SiGe epitaxial growth for strained CMOS Si technology was developed for 65 nm logic technology generation that integrates with Ni silicidation. A 36% device performance improvement for PMOS devices was achieved using this technology. Key process parameters for this technology such as Si recess etch, epitaxial surface preparation, SiGe growth and Ni silicidation are discussed. Experimental results for these process parameters are also presented.

Selective epitaxial growth of SiGe:C for high speed HBTs

The technique of selective epitaxial growth (SEG) of Si, SiGe, and SiGe:C is described in general and with respect to the application in hetero bipolar transistors (HBTs). Advantages like easy fabrication of self-aligned transistor structures are accompanied by a more complicated dependence of layer properties on process conditions in comparison to non-selective growth. Nevertheless, after careful analysis SEG related difficulties have been solved and selectively grown SiGe:C layers are successfully used in high speed HBTs. Good manufacturability and performance of these devices are demonstrated by a high yield and a ring oscillator gate delay as low as 4.7 ps.

Selective epitaxial growth of Si and SiGe for metal oxide semiconductor transistors

We have studied in reduced pressure chemical vapor deposition the selective epitaxial growth (SEG) of Si and SiGe using a dichlorosilane+germane+hydrochloric acid chemistry. We have first of all highlighted the specifics of the SEG of Si on patterned wafers with a dichlorosilane+hydrochloric acid chemistry. We have then dealt with the SEG of SiGe, focusing notably on the so-called loading effects (increase of the SiGe growth rate and of the Ge concentration when switching over from a blanket to a dielectric-masked substrate). Finally, we have studied the thermal stability of typical Si/SiGe/Si stacks versus conventional anneals used nowadays for advanced devices in the microelectronics industry. All this knowledge can be used to selectively grow Si or Si/SiGe/Si stacks inside the Si windows of patterned wafers for the formation of raised sources and drains or for the channel engineering of p-type metal oxide semiconductor transistors.

Excimer Laser-Assisted In Situ Phosphorous Doped Si(1-x)GexEpilayer Activation

This paper presents results from experiments on laser-annealed SiGe-selective epitaxial growth (LA-SiGe-SEG). The SiGe-SEG technology is attractive for devices that require a low band gap and high mobility. However, it is difficult to make such devices because the SiGe and the highly doped region in the SiGe layer limit the thermal budget. This results in leakage and transient enhanced diffusion. To solve these problems, we grew in situ doped SiGe SEG film and annealed it on an XMR5121 high power XeCl excimer laser system. We successfully demonstrated this LA-SiGe-SEG technique with highly doped Ge and an ultra shallow junction on p-type Si (100). Analyzing the doping profiles of phosphorus, Ge compositions, surface morphology, and electric characteristics, we confirmed that the LA-SiGe-SEG technology is suitable for fabricating high-speed, low-power devices.

Si-Ge-H-Cl 계를 이용한 자기정렬 HBT용 Si 및 SiGe의 선택적 에피성장

Low temperature selective epitaxial growth of Si and SiGe has been obtained using an industrial single wafer chemical vapor deposition module operating at reduced pressure. Epitaxial Si and heteroepitaxial SiGe deposition with Ge content about 20 % has been studied as extrinsic base for self-aligned heterojunction bipolar transistors(HBTs), which helps to reduce the parasitic resistance to obtain higher maximum oscillation frequencies(f<TEX>$\_$</TEX>max/). The dependence of Si and SiGe deposition rates on exposed windows and their evolution with the addition of HCl to the gas mixture are investigated. SiH<TEX>$_2$</TEX>Cl<TEX>$_2$</TEX> was used as the source of Si SEG(Selective Epitaxial Growth) and GeH<TEX>$_4$</TEX> was added to grow SiGe SEG. The addition of HCl into the gas mixture allows increasing an incubation time even low growth temperature of 675∼725<TEX>$^{\circ}C$</TEX>. In addition, the selectivity is enhanced for the SiGe alloy and it was proposed that the incubation time for the polycrystalline deposit on the oxide is increased probably due to GeO formation. On the other hand, when only SiGe SEG(Selective Epitaxial Growth) layer is used for extrinsic base, it shows a higher sheet resistance with Ti-silicide because of Ge segregation to the interface, but in case of Si or Si/SiGe SEG layer, the sheet resistance is decreased up to 70 %.

Process Improvements in the Selective Epitaxial Growth of Si1 − xGex / Si Strained Layers in a Conventional Hot‐Wall LPCVD System

Three process considerations were identified as essential for the selective epitaxial growth (SEG) of SiGe in hot‐wall tubular low pressure chemical vapor deposition reactors. A thermodynamic analysis of the system revealed that the hydrogen bake condition for SiGe SEG had to be modified from that for Si SEG to eliminate outgassing of residual Ge, which adversely affected the initial growth surface. A two‐step hydrogen bake was developed to eliminate the problem. A high temperature bake, carried out before wafer loading, removed residual Ge deposited on the reactor wall from the previous run. After wafer loading, removed residual Ge deposited on the reactor wall from the previous run. After wafer loading and purge, a lower temperature bake then removed the native oxide. Second, a selectively grown Si buffer layer improved the initial growth surface for later SiGe SEG. The Si buffer layer covered the remaining native oxide, which the previous hydrogen bake did not totally remove, and reduced the defects at the interface. Finally, a small flow of Si source gas during the temperature ramp down period helped to keep the buffer layer surface clean prior to SiGe SEG. All three steps proved to be essential in obtaining SiGe SEG of higher quality.

Selective epitaxial growth of Ge and SiGe using Si 2H 6 gas and Ge solid source molecular beam epitaxy

Selective epitaxial growth of SiGe on Si(100) substrates with a SiO 2 mask was successfully achieved by Si 2H 6 gas and Ge solid source molecular beam epitaxy (Si 2H 6-Ge MBE), and the properties and the mechanism are presented for the first time. The incubation times and the critical thicknesses of SiGe and Si were studied at growth temperatures of 575 to 630°C. The critical thickness of SiGe was the same as that of Si using Si 2H 6. The mechanism of the SiGe selective epitaxial growth by this method has been clarified. The Ge selective epitaxial growth was also performed at a temperature of 610°C. Two nucleation mechanisms of SiGe on SiO 2 layers were proposed.