Abstract
Selective Epitaxial Growth of SiGe and/or Si-cap/SiGe heterostructures offer an elegant way to improve pMOS device performance. This paper discusses some important challenges and characteristics of the corresponding epi process. Loading effects are strongly reduced by choosing the growth conditions away from the mass transport regime, i.e. by reducing the growth pressure and/or increasing the gas velocity. Anomalous SiGe thickening at convex corners of recessed areas and the impact of the underlying SiGe on the growth behavior during Si- capping are discussed as well. The limits of the chemical and thermal budgets during pre-epi treatments as defined by the device concepts require some process optimization but are not a show stopper.
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