SiGe Heterojunction Bipolar Transistors Research Articles

Investigation of cryogenic current–voltage anomalies in SiGe HBTs: Role of base–emitter junction inhomogeneities

The deviations of cryogenic collector current–voltage characteristics of SiGe heterojunction bipolar transistors (HBTs) from ideal drift-diffusion theory have been a topic of investigation for many years. Recent work indicates that direct tunneling across the base contributes to the non-ideal current in highly scaled devices. However, cryogenic discrepancies have been observed even in older-generation devices for which direct tunneling is negligible, suggesting that another mechanism may also contribute. Although similar non-ideal current–voltage characteristics have been observed in Schottky junctions and were attributed to a spatially inhomogeneous junction potential, this explanation has not been considered for SiGe HBTs. Here, we experimentally investigate this hypothesis by characterizing the collector current ideality factor and built-in potential of a SiGe HBT vs temperature using a cryogenic probe station. The temperature dependence of the ideality factor and the relation between the built-in potential as measured by capacitance–voltage and current–voltage characteristics are in good qualitative agreement with the predictions of a theory of electrical transport across a spatially inhomogeneous junction. These observations suggest that inhomogeneities in the base–emitter junction potential may contribute to the cryogenic non-idealities. This work helps to identify the physical mechanisms limiting the cryogenic microwave noise performance of SiGe HBTs.

Simple Modeling and Analysis of Total Ionizing Dose Effects on Radio-Frequency Low-Noise Amplifiers

In this study, the degradation characteristics of radio frequency (RF)-low-noise amplifiers (LNA) due to a total ionizing dose (TID) is investigated. As a device-under-test (DUT), sample LNAs were prepared using silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) as core elements. The LNA was based on a cascode stage with emitter degeneration for narrowband applications. By using a simplified small-signal model of a SiGe HBT, design equations such as gain, impedance matching, and noise figure (NF) were derived for analyzing TID-induced degradations in the circuit-level performance. To study radiation effects in circuits, the SiGe-RF-LNAs fabricated in a commercial 350 nm SiGe technology were exposed to 10-keV X-rays to a total ionizing dose of up to 3 Mrad(SiO2). The TID-induced performance changes of the LNA were modeled by applying degradation to device parameters. In the modeling process, new parameter values after irradiation were estimated based on information in the literature, without direct measurements of SiGe HBTs used in the LNA chip. As a result, the relative contributions of parameters on the circuit metrics were compared, identifying dominant parameters for degradation modeling. For the TID effects on input matching (S11) and NF, the base resistance (RB) and the base-to-emitter capacitance (Cπ) of the input transistor were mostly responsible, whereas the transconductances (gm) played a key role in the output matching (S22) and gain (S21). To validate the proposed approach, it has been applied to a different LNA in the literature and the modeling results predicted the TID-induced degradations within reasonable ranges.

Investigation of laser-induced single event effect on SiGe BiCMOS low noise amplifiers

With the further development of the complementary metal-oxide-semiconductor (CMOS) technology and the silicon-germanium (SiGe) epitaxy technology, SiGe bipolar CMOS (BiCMOS) low noise amplifiers (LNAs) are widely used in the first level of radio frequency (RF) transceiver system in space. The core part of SiGe BiCMOS LNA is SiGe heterojunction bipolar transistor (SiGe HBT) which naturally possesses excellent temperature characteristic and favorable build-in total ionizing dose and displacement damage resistance without any radiation hardening. However, the single event effect caused by the transient charge collection is the bottleneck problem, restricting its application in space. In this work, laser microbeam experiments were carried out on a SiGe BiCMOS LNA in which the sensitive region of single event effect was located. The experimental results indicate that the transient charge collection of SiGe HBT is the main reason of the single event effect of SiGe BiCMOS LNA. TCAD simulations show that the ionization track caused by ion incident in CMOS region will cross the deep trench isolation (DTI) structure, generate electron-hole pairs in SiGe HBT region and cause transient charge collection. The circuit simulations by ADS show that the peak value of the transient voltage will drop sharply when the SEE pulse transient voltage crosses the capacitor between the first stage and the second stage, which indicates that the capacitor plays an important role in transmitting the transient pulses caused by single event effect. The experimental and simulation results in this work provide technical support for radiation hardening by design (RHBD) of the single event effect of SiGe BiCMOS LNA.

Transient dose rate effects in silicon–germanium heterojunction bipolar transistors

Transient γ-radiation and laser-simulated experiments were carried out to investigate the transient dose rate effect (TDRE) in SiGe heterojunction bipolar transistors (HBTs) for the first time. The results indicate that IBM43RF0100 SiGe HBTs experience a significant sensitivity of TDRE. For the laser-simulated experiment, the duration of transient current and charge collection are matched well with that of transient γ-radiation. The amplitude of transient photocurrent induced by the lower energy order of μJ approaches the transient photocurrent induced by transient γ-radiation. It is demonstrated that laser-simulated experiments are a candidate and a convenient method to evaluate the TDRE response of SiGe HBTs, which avoids serious electromagnetic interference in the transient γ-radiation environment.

Wideband SiGe-HBT Low-Noise Amplifier with Resistive Feedback and Shunt Peaking.

In this work, the design of a wideband low-noise amplifier (LNA) using a resistive feedback network is proposed for potential multi-band sensing, communication, and radar applications. For achieving wide operational bandwidth and flat in-band characteristics simultaneously, the proposed LNA employs a variety of circuit design techniques, including a voltage-current (shunt-shunt) negative feedback configuration, inductive emitter degeneration, a main branch with an added cascode stage, and the shunt-peaking technique. The use of a feedback network and emitter degeneration provides broadened transfer characteristics for multi-octave coverage and a real impedance for input matching, respectively. In addition, the cascode stage pushes the band-limiting low-frequency pole, due to the Miller capacitance, to a higher frequency. Lastly, the shunt-peaking approach is optimized for the compensation of a gain reduction at higher frequency bands. The wideband LNA proposed in this study is fabricated using a commercial 0.13 μm silicon-germanium (SiGe) BiCMOS process, employing SiGe heterojunction bipolar transistors (HBTs) as the circuit's core active elements in the main branch. The measurement results show an operational bandwidth of 2.0-29.2 GHz, a noise figure of 4.16 dB (below 26.5 GHz, which was the measurement limit), and a total power consumption of 23.1 mW under a supply voltage of 3.3 V. Regarding the nonlinearity associated with large-signal behavior, the proposed LNA exhibits an input 1-dB compression (IP1dB) point of -5.42 dBm at 12 GHz. These performance numbers confirm the strong viability of the proposed approach in comparison with other state-of-the-art designs.

Neuroevolution-Based Network Architecture Evolution in Semiconductor Manufacturing.

Promoted model architectures or algorithms are crucial for intelligent manufacturing since developing them takes a lot of trial and error to embed the domain knowledge into the models correctly. Especially in semiconductor manufacturing, the whole processes depend on complicated physical equations and sophisticated fine-tuning. Therefore, we use a neuroevolution-based model to search the optimized architecture automatically. The collector current value at a particular bias of the silicon-germanium (SiGe) heterojunction bipolar transistor, generated by technology computer-aided design (TCAD), is used as the target dataset with six process parameters as the inputs. The processes include oxidation, dry and wet etching, implantation, annealing, diffusion, and chemical-mechanical polishing. Our work can build a suitable model network with a fast turnaround time, and practical physical constraints are fused in it without domain knowledge extraction. Take the case with 3840 data and one output as an instance. The mean square errors of the train set and validation set, as well as the mean absolute percentage error of the test set, are 1.317 × 10-6, 7.215 × 10-7, and 0.216 while using multilayer perceptron (MLP) and they are 3.285 × 10-7, 1.661 × 10-7, and 0.097 while using NE. The consequences show that the work in this vein is promising. According to the trend plot and results, the ability to extract physic is much better than the traditional (MLP) model.

Impact of Device Layout on Thermal Parameters and RF Performance of 90-nm SiGe HBTs

The present work investigates the impact of transistor layout on both the RF and thermal performance of 90-nm SiGe heterojunction bipolar transistors (HBTs). The resulting performance shows only slight degradation in small-signal RF figures-of-merit, while large-signal RF figures-of-merit relevant to power amplifiers (PAs) are improved. Thermal resistance and capacitance were extracted for five different SiGe HBT layouts with the same total emitter area. Additionally, a favorable trade-off exists between RF performance figures-of-merit and thermal parameters; namely, the thermal time constant can be reduced by up to 37% with optimal layout, with only slight degradation (up to 8%) in RF performance. These optimal device layout variations can help circuit designers mitigate thermal memory effects at the device level, thereby improving the overall large-signal linearity of PAs.

Effects of Different Factors on Single Event Effects Introduced by Heavy Ions in SiGe Heterojunction Bipolar Transistor: A TCAD Simulation

In this paper, the effects of different factors, including the heavy ions striking location, incident angle, linear energy transfer (LET) value, projected range, ambient temperature and bias state, on the single event transient introduced by heavy ions irradiation in the SiGe heterojunction bipolar transistor (HBT) were investigated by the TCAD simulation. The results show that the current transient peak value, collected charge and carrier type of each terminal are changed by the striking location, incident angle and bias state. The current transient peak value and collected charge increase with the LET value, while they decrease with the ambient temperature. When heavy ions vertically irradiate the collector and substrate, the current transient peak value and collected charge increase with the projected range; therefore, the species of heavy ions should be considered in studying the single event effects of the SiGe HBT induced by heavy ions irradiation. The microphysical mechanism of these factors influencing the single event effects of the SiGe HBT is discussed in this work.

A Physics-Based Analytical Formulation for the Tunneling Current Through the Base of Bipolar Transistors Operating at Cryogenic Temperatures

A physics-based analytical solution for the direct tunneling current through the base region of bipolar transistors operating at cryogenic temperatures (CTs) is derived. The obtained formulation is continuously differentiable over the entire bias region and contains only few experimentally determinable model parameters, which makes it well-suited for compact circuit modeling. Very good agreement of the new formulation with both a numerical evaluation of the tunneling current integral and experimental data of two silicon–germanium (SiGe) heterojunction bipolar transistor (HBT) process generations is demonstrated.

Design and Simulation of a Novel Hetero-junction Bipolar Transistor with Gate-Controlled Current Gain

A new structure for SiGe Hetero-junction Bipolar transistor (HBT) is designed and simulated using Silvaco simulator. The considered extra terminal gives the ability to control the transistor's current gain. By applying voltage to the gate terminal, the base effective width would be controlled. Decrement of the Base width yields to the carrier recombination rate reduction, let the emitted electrons to have higher chance to reach the collector. Considering extra terminal have two approaches. One is to improve the current gain of the transistor by applying a constant voltage to the gate and the other is to modify the characteristics of the transistor in such a way that the current gain became optimized. The current gain of the transistor without any gate voltage is about 50V, which increases to 750 for high and 50,000 for low collector currents with the gate voltage variation consideration. In addition, our final proposed gate-controlled HBT with a large gate over the base and collector has the breakdown voltage of 8V and the cut-off frequency of about 11 GHz. The maximum FoM of 1200 is achieved using the proposed structure.

Optimisation of extrinsic base doping of a SiGe heterojunction bipolar transistor integrated in a BiCMOS 55 nm technology for high frequency performances

Optimisation of extrinsic base doping of a SiGe heterojunction bipolar transistor integrated in a BiCMOS 55 nm technology for high frequency performances

Silicon-Germanium Heterojunction Bipolar Transistor DC and AC Analysis Operating under Cryogenic Temperature

In this work, the numerical simulation of a SiGe heterojunction bipolar transistor (HBT) for DC and AC performance operating at cryogenic temperature with a hydrodynamic carrier transport model is analyzed. A new modified temperature-dependent Si1−xGex energy bandgap model was used. Using a simplified 2D TCAD design structure, the device characteristics on 55 nm SiGe HBT technology and the mobility model are calibrated with experimental data. Base current reversal due to induced impact-ionization at the collector-base junction is analyzed, where the estimated collector-emitter breakdown voltage with the base open (BVCEO) is 1.48 V at 300 K. This reveals good voltage handling ability. At cryogenic temperatures, dopant incomplete ionization in the lightly doped collector region shows a 28% decrease in ionized dopant concentration at 50 K; this affects the base-collector depletion capacitance. The emitter electron barrier tunneling leakage on collector current is studied using a non-local e-barrier tunneling model at different temperatures that shows an improvement in peak DC gain at lower temperatures. Using the small-signal ac analysis, the cut-off frequency and the maximum oscillation frequency are extracted for high-frequency application, and the base widening effect is discussed. A comparison of this work with measured data on 90 nm SiGe HBT is also discussed in brief, which shows improvements in the simulated structure.

Temperature dependence of single-event transients in SiGe heterojunction bipolar transistors for cryogenic applications

We experimentally demonstrate that the dominant mechanism of single-event transients in silicon-germanium heterojunction bipolar transistors (SiGe HBTs) can change with decreasing temperature from +20 °C to −180 °C. This is accomplished by using a new well-designed cryogenic experimental system suitable for a pulsed-laser platform. Firstly, when the temperature drops from +20 °C to −140 °C, the increased carrier mobility drives a slight increase in transient amplitude. However, as the temperature decreases further below −140 °C, the carrier freeze-out brings about an inflection point, which means the transient amplitude will decrease at cryogenic temperatures. To better understand this result, we analytically calculate the ionization rates of various dopants at different temperatures based on Altermatt’s new incomplete ionization model. The parasitic resistivities with temperature on the charge-collection pathway are extracted by a two-dimensional (2D) TCAD process simulation. In addition, we investigate the impact of temperature on the novel electron-injection process from emitter to base under different bias conditions. The increase of the emitter–base junction’s barrier height at low temperatures could suppress this electron-injection phenomenon. We have also optimized the built-in voltage equations of a high current compact model (HICUM) by introducing the impact of incomplete ionization. The present results and methods could provide a new reference for effective evaluation of single-event effects in bipolar transistors and circuits at cryogenic temperatures, and could provide a new evidence of the potential of SiGe technology in applications in extreme cryogenic environments.

A laser source driver in 0.18 μm SiGe BiCMOS technology for high speed quantum key distribution

Quantum key distribution (QKD) has rapidly developed recently. The repetition frequency of the QKD system increases from tens or hundreds of MHz to GHz. A laser diode (LD) operating in gain-switched mode is widely used as a weak coherent light source in a QKD system. We present an LD driver circuit fabricated in 0.18 μm SiGe heterojunction bipolar transistor bipolar complementary metal oxide semiconductor technology. The circuit can operate at frequencies up to 2.5 GHz, satisfying the requirements of high-speed laser drives in practical QKD systems. The output current of the driver circuit can reach 100 mA when driving an LD whose input equivalent resistance is ∼21 Ω. The extinction ratio of the 1550-nm distributed feedback LD light source driven by our driver circuit reaches 23 dB at the operating frequency of 2.5 GHz, meeting the requirements of QKD systems. This circuit will be used in miniaturized QKD systems.

Challenges for Sige Bicmos in Advanced-Node SOI

D-band (110-170GHz) spectrum is gaining attention for various applications, including 6G mm-Wave, sub-THz sensing, and radar. These systems require lattice spacing for antenna elements at sub-1mm and a very low loss signal path from antenna to integrated chip. A highly efficient front-end in a very small form factor will be required for these systems. This drives the requirement for a monolithically integrated high-gain, high-efficiency front-end that also leverages the benefits of a high-speed / high-density digital CMOS. Silicon germanium (SiGe) heterojunction bipolar transistors (HBT) integrated along with a high-density CMOS provide such an all-silicon monolithic solution.The US government is fostering the expansion of “unique and differentiated domestic manufacturing” with funding through DARPA’s Technologies for Mixed-mode Ultra Scaled Integrated Circuits (T-MUSIC) [1] program to enable disruptive RF mixed-mode technologies by developing high performance RF analog integrated with advanced digital CMOS. Through the T-MUSIC program, DARPA seeks to: 1) advance RF and mixed-mode devices to support ultra-wideband RF frontends from HF to 100 GHz; 2) integrate those devices with high density digital CMOS electronics at the wafer scale to enable embedded digital intelligence; 3) develop and explore ultra-high resolution broadband mixed-mode circuit building blocks for DoD-relevant applications; 4) explore innovative device topologies and materials to form THz devices in an advanced digital CMOS fabrication platform; and 5) establish a domestic ecosystem that facilitates enduring DoD access to differentiated capabilities for high performance RF mixed-mode SoCs.Under T-MUSIC, GlobalFoundries is demonstrating BiCMOS on 45nm PDSOI, which is the focus of this paper, and 22nm FDSOI CMOS with goals of increasing HBT performance of fT/fMAX from 350/500 GHz to 400/600 GHz and 600/700 GHz. HBTs with fT/fMAX of 380/550GHz GHz have been demonstrated building upon previously published results [2]. This paper will touch on some of the challenges that were encountered in achieving that result and discuss those anticipated in future work.Achieving these results required scaling transistor dimensions. Vertical scaling of the emitter, base and collector layers, with higher doping concentrations, reduces transit time but results in higher current densities and higher electric fields. Lateral scaling of the transistor structure reduces parasitic capacitance and resistance but concentrate the power dissipation in a smaller area. The thermal conductivity of silicon is 148W/m-K whereas that of silicon dioxide is ~1.4W/m-K. Even a thin layer of oxide will significantly increase the self-heating of the HBT. Therefore, we replace the SOI with coplanar epitaxy in regions where the HBTs are formed.The vertical scaling of the HBT requires limiting the thermal cycles that the HBT will experience during processing and suggests forming the HBT as late as possible in the CMOS process. However, the thermal cycles associate with the epitaxy and film depositions to form the HBT impact the CMOS transistors which suggests forming the HBT early in the process. We found a point in the process that offers the best compromise minimizing the impact to the doped-channel PDSOI CMOS while achieving the HBT performance goals. Work is just beginning on integration tradeoffs for FDSOI with metal gate and high-K dielectrics.Advanced-node CMOS processes can form components having smaller dimensions which offers advantages for lateral scaling but also presents challenges for forming the HBT. The contact height in 45nm is significantly less than the height of the HBT structure used in GF’s 9HP process. We changed the formation of the emitter and base so that the emitter and base contacts are almost coplanar in contrast to 9HP where the emitter was almost twice the height of the base. This problem is being further exasperated as we migrate to 22nm.The shrinking of BEOL wiring dimensions, along with the ability of the HBT to drive high currents, presents challenges in designing within limits imposed by electromigration. The use of wider wires is constrained by metal density rules. The use of stacked metal levels and redundant vias impact the parasitic capacitances and resistances of the interconnects.The paper and presentation will review these, and other challenges encountered in achieving BiCMOS integration of SiGe HBTs with fT/fMAX of 380/550GHz GHz [see figure] on a 45nm PDSOI CMOS and touch future work.This research was developed with funding from the Defense Advanced Research Projects Agency (DARPA) and is Approved for Public Release, Distribution Unlimited. The views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.[1] https://www.darpa.mil/attachments/T-MUSIC_Proposers%20Day_Presentations_Combined.pdf [2] J. Pekarik et al., 2021 IEEE BCICTS, 2021, pp. 1-4, Figure 1

Wideband SiGe down-converter for millimeter-wave radio astronomy applications

A Q-band down-converter module with high conversion gain (CG) is presented for a wideband radio astronomy receiver. This down-converter module is designed on a silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) process (0.13 μm) to realize high CG, low LO power operation, and wideband frequency impedance matching for RF/LO/IF ports. The down-converter consists of a double-balanced Gilbert mixing core with on-chip RF/LO transformer baluns, an IF buffer, and bandpass filter. The performance of the down converter is largely dependent on the passive components and signal line interconnection. The design of all passive structures is analyzed and optimized with FEM simulations for a high-quality factor to minimize losses and parasitic effects. This module achieves 8 dB of CG at a low LO power of −6 dBm over a wide RF bandwidth from 28 to 56 GHz and IF bandwidth from 6 to 18 GHz. It demonstrates LO-to-IF/LO-to-RF/RF-to-IF isolations > dB / 40 dB/35 dB, respectively. The critical FEM simulation is described in the design of this high-density SiGe HBT RF circuit. The measured performance confirms the simulation results. The module meets the original design requirements of the DVA-2 Q-band receiver.

Sensitivity study of the SiGe heterojunction bipolar transistor single event effect based on pulsed laser and technology computer-aided design simulation

The single event effect of a silicon–germanium heterojunction bipolar transistor (SiGe HBT) was thoroughly investigated. By considering the worst bias condition, the sensitive area of the proposed device was scanned with a pulsed laser. With variation of the collector bias and pulsed laser incident energy, the single event transient of the SiGe HBT was studied. Moreover, the single event transient produced by laser irradiation at a wavelength of 532 nm was more pronounced than at a wavelength of 1064 nm. Finally, the impact of the equivalent linear energy transfer of the 1064 nm pulsed laser on the single event transient was qualitatively examined by performing technology computer-aided design simulations, and a good consistency between the experimental data and the simulated outcomes was attained.

Microscopic Simulation of the RF Performance of SiGe HBTs With Additional Uniaxial Mechanical Stress

A very detailed investigation of high-speed silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) showed an underestimation of the measured peak cutoff frequency by simulations with a hydrodynamic (HD) model. It was speculated that this might be due to a breakdown of the HD approximation or unknown additional mechanical stress. We repeated those simulations with the more fundamental Boltzmann transport equation (BTE) based on the same device model (doping profiles, 2-D geometry, parasitics, and so on) and obtained almost similar results showing that this failure was not due to a breakdown of the HD approximation. Since additional uniaxial stress along the direction of the lateral base has been shown to increase the cutoff frequency, we investigated this effect. We found by 2-D device simulations that the increase in the peak cutoff frequency is rather small, and at high stress levels, it even decreases, if the uniaxial stress is applied homogenously. This is due to the reduction of the conductivity of the highly doped collector layer by the stress. If the stress is limited to the intrinsic transistor, the increase in the cutoff frequency is monotonic with growing stress. On the other hand, the collector current for a given base–emitter voltage also increases with stress leading to an overestimation of the collector current compared with the measurements. If this increase is corrected by a slight decrease in the germanium profile, the gain in the peak cutoff frequency is lost. Thus, the underestimation of the peak cutoff frequency cannot be explained by an additional homogeneous uniaxial stress in the intrinsic transistor.

Methods for Extracting the Temperature- and Power-Dependent Thermal Resistance for SiGe and III-V HBTs From DC Measurements: A Review and Comparison Across Technologies

Many different methods have been proposed in the literature for the extraction of the thermal resistance of heterojunction bipolar transistors (HBTs). This review presents a detailed evaluation and discussion of several widely used methods. Special emphasis is put on a generalized analysis of the underlying assumptions, suitable operating point range, and necessary measurement effort of each method. The accuracy of each method is determined by applying it to data based on circuit simulations of advanced SiGe and III-V HBT technologies. Experimental data from those technologies are used to highlight practical issues. A guideline for the selection of the most suitable method in practice is also given.

Voltage-Controlled Oscillator Utilizing Inverse-Mode SiGe-HBT Biasing Circuit for the Mitigation of Single-Event Effects

The advantages and the tradeoffs associated with the use of inverse-mode (IM) silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) biasing circuitry in radio-frequency (RF) voltage-controlled oscillators (VCOs) have been investigated and the performance of proposed VCOs (IM VCOs) is compared with VCOs with conventional forward-mode (FM) SiGe-HBTs (FM VCOs). Where the high-frequency performance of IM VCOs is inevitably degraded due to unfavorable device optimization unlike FM VCOs, IM VCOs provide acceptable low-GHz VCO circuit performance. In terms of single-event effects (SEEs), the IM VCOs show reduced transient peaks and duration in comparison with conventional FM VCOs. In addition, the performance of the VCOs is analyzed in terms of transient error vector magnitude (TEVM) in an RF receiver (RX) using quadrature phase-shift keying (QPSK) modulation under a radiation environment. The IM VCOs in the RX circuit show better reliability under SEEs, offering 28.2% lower TEVM at a 64 Mb/s data rate, than that of the RX circuit with conventional FM VCOs. Therefore, the application of IM SiGe-HBT biasing circuits for RF VCOs can be a viable SEE-hardening technique for space-based RF systems. The VCO prototype was fabricated using IHP 130-nm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology.