Impact of Device Layout on Thermal Parameters and RF Performance of 90-nm SiGe HBTs

Abstract

The present work investigates the impact of transistor layout on both the RF and thermal performance of 90-nm SiGe heterojunction bipolar transistors (HBTs). The resulting performance shows only slight degradation in small-signal RF figures-of-merit, while large-signal RF figures-of-merit relevant to power amplifiers (PAs) are improved. Thermal resistance and capacitance were extracted for five different SiGe HBT layouts with the same total emitter area. Additionally, a favorable trade-off exists between RF performance figures-of-merit and thermal parameters; namely, the thermal time constant can be reduced by up to 37% with optimal layout, with only slight degradation (up to 8%) in RF performance. These optimal device layout variations can help circuit designers mitigate thermal memory effects at the device level, thereby improving the overall large-signal linearity of PAs.