SiGe Heterojunction Bipolar Transistor Technology Research Articles

Silicon-Germanium Heterojunction Bipolar Transistor DC and AC Analysis Operating under Cryogenic Temperature

In this work, the numerical simulation of a SiGe heterojunction bipolar transistor (HBT) for DC and AC performance operating at cryogenic temperature with a hydrodynamic carrier transport model is analyzed. A new modified temperature-dependent Si1−xGex energy bandgap model was used. Using a simplified 2D TCAD design structure, the device characteristics on 55 nm SiGe HBT technology and the mobility model are calibrated with experimental data. Base current reversal due to induced impact-ionization at the collector-base junction is analyzed, where the estimated collector-emitter breakdown voltage with the base open (BVCEO) is 1.48 V at 300 K. This reveals good voltage handling ability. At cryogenic temperatures, dopant incomplete ionization in the lightly doped collector region shows a 28% decrease in ionized dopant concentration at 50 K; this affects the base-collector depletion capacitance. The emitter electron barrier tunneling leakage on collector current is studied using a non-local e-barrier tunneling model at different temperatures that shows an improvement in peak DC gain at lower temperatures. Using the small-signal ac analysis, the cut-off frequency and the maximum oscillation frequency are extracted for high-frequency application, and the base widening effect is discussed. A comparison of this work with measured data on 90 nm SiGe HBT is also discussed in brief, which shows improvements in the simulated structure.

Terahertz Signal Source and Receiver Operating Near 600 GHz and Their 3-D Imaging Application

In this article, a set of oscillators and a heterodyne image receiver operating near 600 GHz have been developed, each based on a 250-nm InP heterojunction bipolar transistor (HBT) technology and a 130-nm SiGe HBT technology, respectively. The oscillators are based on the common-base cross-coupled push–push topology, which employed coupled-line loads for improved output power and efficiency with a small area. The measured oscillation frequency ranges of the three oscillators with different coupled-line lengths were 628–682, 556–610, and 509–548 GHz, respectively, with a tuning capability achieved with bias variation. The maximum output power and the dc-to-RF efficiency achieved with the oscillators were −10 dBm and 0.19%, respectively. The heterodyne receiver, which consists of a mixer, an IF amplifier, and an IF detector, exhibited a maximum responsivity of 469 kV/W and a minimum noise equivalent power (NEP) of 0.64 pW/Hz1/2. A transmission-mode 3-D THz tomography imaging setup was established with one of the fabricated oscillators and the heterodyne receiver employed as the signal source and the image detector, respectively. With the imaging setup, a successful reconstruction of 3-D images of a target object was demonstrated based on the filtered back-projection algorithm.

Design and Analysis of fT-Doubler-Based RF Amplifiers in SiGe HBT Technology

For performance-driven systems such as space-based applications, it is important to maximize the gain of radio-frequency amplifiers (RFAs) with a certain tolerance against radiation, temperature effects, and small form factor. In this work, we present a K-band, compact high-gain RFA using an fT-doubler topology in a silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) technology platform. The through-silicon vias (TSVs), typically used for small-size chip packaging purposes, have been effectively utilized as an adjustable matching element for input impedance, reducing the overall area of the chip. The proposed RFA, fabricated in a modest 0.35 µm SiGe technology, achieves a gain of 14.1 dB at 20 GHz center frequency, and a noise figure (NF) of 11.2 dB at the same frequency, with a power consumption of 3.3 mW. The proposed design methodology can be used for achieving high gain, avoiding a complex multi-stage amplifier design approach.

Mitigation of Single-Event Effects in SiGe-HBT Current-Mode Logic Circuits.

It has been known that negative feedback loops (internal and external) in a SiGe heterojunction bipolar transistors (HBT) DC current mirrors improve single-event transient (SET) response; both the peak transient current and the settling time significantly decrease. In the present work, we demonstrate how radiation hardening by design (RHBD) techniques utilized in DC bias blocks only (current mirrors) can also improve the SET response in AC signal paths of switching circuits (e.g., current-mode logic, CML) without any additional hardening in those AC signal paths. Four CML circuits both with and without RHBD current mirrors were fabricated in 130 nm SiGe HBT technology. Two existing RHBD techniques were employed separately in the current mirrors of the CML circuits: (1) applying internal negative feedback and (2) adding a large capacitor in a sensitive node. In addition, these methods are also combined to analyze the overall SET performance. The single-event transients of the fabricated circuits were captured under the two-photon-absorption laser-induced single-event environment. The measurement data clearly show significant improvements in SET response in the AC signal paths of the CML circuits by using the two radiation hardening techniques applied only in DC current mirrors. The peak output transient current is notably reduced, and the settling time upon a laser strike is shortened significantly.

Fast timing monolithic silicon pixel sensor for TOF-PET

The Thin-TOF PET (TT-PET) project aims at the construction of a small-animal PET scanner based on silicon monolithic pixel sensors with 30ps time resolution for 511keV photons, equivalent to 100ps time resolution for minimum ionizing particles. The high time resolution of the pixel sensor allows for precise time of flight measurement of the two photons and a significant improvement in the signal-to-noise ratio of images. The TT-PET scanner also has sensitivity for photon depth of interaction, thus improving the spatial resolution across the whole view of the scanner. The performance of the scanner estimated by a GEANT4 Monte Carlo simulation is presented. In order to achieve the high time resolution, the SiGe heterojunction bipolar transistor technology (SG13S from IHP) was chosen for fast integration, low equivalent noise charge and low power consumption. TCAD simulations were used to design the appropriate guard rings for the pixel sensor. Laboratory measurements of the first test chip show the correct functionality of the guard ring up to a bias potential of 200V applied to the pixels and a good signal-to-noise ratio for the detection of electrons from a 90Sr source. A test beam measurement with an un-thinned chip shows more than 99% efficiency and approximately 200ps time resolution for minimum ionizing particles despite the absence of wafer thinning and post-processing.

(Invited) Bicmos Technology Optimization for Millimeter Wave Applications

With the progress of RF CMOS and BiCMOS technologies, millimeter-wave applications have come well within reach of silicon-based technologies [1-3]. NXP’s SiGe BiCMOS process offers a 0.25μm CMOS base-line, with shallow- and deep-trench isolation, a full suite of high-quality passive components and three SiGe:C Heterojunction Bipolar Transistors. From the first publication on the 8th generation [4], the process architecture has only been changed cautiously, keeping manufacturability and cost very competitive. A good example of that is the addition of the third HBT with a high-energy implanted subcollector [5], bringing the typical BVCBO breakdown voltage range from 4.5V to 11.5 to 15V for the Low Voltage, High Voltage and Extended High Voltage device respectively. Generation 9 was first published in 2015 [6], with main features illustrated in Figs. 1 and 2. Since then, the process has been used to further explore millimeter-wave application needs. In this paper, we focus on improving noise performance at frequencies above 28GHz by scaling the npn in the vertical direction, i.e. the doping profiles, but also scaling in the lateral direction to reduce all parasitic elements. In the early nineties device fabrication using epitaxial growth of strained SiGe/Si heterostructures enabled a breakthrough in bipolar process technology. Nanometer-scale bandgap engineering of SiGe:C Heterojunction Bipolar Transistors have pushed fT/fMAX performances above 500GHz. In our technology today, non-uniformity of the thicknesses of the individual layers has been brought below 5Å, matched across a number of epi reactors in two different fabs. After growing the desired npn doping profile with such great care and precision, the total thermal budget of the BiCMOS process and all its options, determines to a great extent what performance is left of the intrinsic doping profile capability. The noise performance of a Low Noise Amplifier (LNA) depends on the minimum noise figure NFMIN=10log(FMIN) of the SiGe Heterojunction Bipolar Transistor (HBT), which in turn depends on a number of technology related device parameters, see Equation (1), [7]. F = 1 + 1/hFE + { 1/hFE + (2gmRB) (1/hFE + (f/fT)2 ) }1/2 ( 1 ) Building on the excellent base resistance properties of the non-selectively grown SiGe:C base architecture of Gen9, we have investigated in this work the effect of reducing the total temperature budget to enable shorter delay times. In a first experiment the final activation anneal was reduced in 5 steps to provide input on re-tuning of the thicknesses in the base-epi stack. From known correlations between inline ellipsometry and process control measurements like, for example reverse emitter-base breakdown voltage shown in Fig. 3, the temperature decrease on the activation anneal could be calculated to correspond with a delta of around 65Å on the emitter cap. This effect, due largely to decreased in-diffusion of arsenic from the mono-emitter, is confirmed by TCAD simulations, as shown in Fig. 4. Similarly, the reduced lateral diffusion of arsenic underneath the L-shaped inside spacers enables re-scaling of the inside spacer width at the bottom of the emitter window to decrease its contribution to the total base resistance. Figure 5 shows the measured minimum noise figure at 30GHz as a function of collector current density for devices with 0.3µm emitter width. It shows the improvement from Gen8 to Gen9 technology, due in this work, to both increased RF performance due to vertical scaling in combination with reductions of the extrinsic base resistance contributions. In conclusion, NXP’s present 0.25µm SiGe BiCMOS processes are suitable for a wide variety of applications and frequency ranges. Process optimization targeted at low noise above 28GHz demonstrates noise performance levels that can easily match processes which feature HBT’s with much higher specified fT/fMAX. References – [1] J.J. Pekarik et al., “A 90nm SiGe BiCMOS technology for mm-wave and high-performance analog applications”, Proc. BCTM, pp. 92-95, 2014. [2] M. Schröter et al., “SiGe HBT technology: future trends and TCAD-based roadmap”, Proc. IEEE, Vol. 105, No. 6, June 2017. [3] B. Heinemann et al., “SiGe HBT with fT/fmax of 505 GHz/720 GHz”, IEDM 2016, pp. 3.1.1-3.1.4. [4] W.D. van Noort et al., “BiCMOS technology improvements for microwave application”, Proc. BCTM, pp. 93-96, 2008. [5] H. Mertens et al., “Extended High Voltage HBTs in a high-performance BiCMOS process”, Proc. BCTM, pp. 158-161, 2011. [6] J. Melai et al., “QUBiC generation 9, a new BiCMOS process optimized for mmWave applications”, Proc. BCTM, pp. 113-116, 2015. [7] See e.g. chapter 7 in J.D. Cressler and G. Niu, “Silicon-Germanium Heterojunction Bipolar Transistors”, Artech House, ISBN 1-58053-361-2, 2003. Figure 1

A 219–266 GHz LO-tunable direct-conversion IQ receiver module in a SiGe HBT technology

AbstractThis paper presents a fully-integrated direct-conversion fundamentally-operated mixer-first quadrature receiver module with a tunable LO in the 219–266 GHz band. It has been implemented in a 0.13-μm SiGe heterojunction bipolar transistor technology. It includes an on-chip LO path driven externally from the printed circuit board (PCB) connector level at 13.6–16.7 GHz. A hybrid coupler generates the quadrature LO signal, which drives a pair of double-balanced fundamentally-operated down-conversion mixers, whose RF ports are connected to a wideband lens-integrated on-chip ring antenna. The chip-on-lens assembly is placed in the recess of a high-speed PCB and wire-bonded. To compensate the inductive behavior of the wire-bond interconnection between the chip and the PCB at the high-speed IF outputs, an on-board 8-section step-impedance low-pass filter has been implemented. The module shows a 47 GHz 3-dB radio frequency/local oscillator operation bandwidth (BW), a peak conversion gain of 7.8 dB, a single-side-band noise figure of 11.3 dB, and a 3-dB IF BW of 13 GHz. The in-phase and quadrature amplitude imbalance stays below 1.58 dB for the 210–280 GHz band. The down-conversion and the baseband stages consume together 75.5 mW, while the LO path 378 mW. The maximum data-rate achieved with this receiver in combination with the transmitter presented in [1–3] is 60 Gbps for quadrature phase shift keying modulation.

96 GHz 4.7 mW low‐power frequency tripler with 0.5 V supply voltage

Using forward-biased base–collector voltage (VBC) in high-speed circuits is usually not attractive due to the performance degradation compared with biasing heterojunction bipolar transistors (HBTs) in the forward-active region. However, the use of ultra-low supply voltage in millimetre-wave circuits provides an interesting application scenario not only for demonstrating the potential of modern silicon germanium (SiGe) HBT technologies in implementing severely power-constrained wireless circuits on silicon but also for verifying the accuracy of compact models beyond standard characteristics typically measured by foundries. The results of a 96 GHz frequency tripler deliberately designed with a reduced supply voltage (0.5 V) in a 130 nm SiGe HBT technology are presented. With only 4.7 mW DC power consumption, this frequency tripler achieves a conversion loss of 3.8 dB, generating a 96 GHz output signal with only −10 dBm input signal at 32 GHz. The impact of transistor series resistances on the tripler performance is also analysed.

A 210–270-GHz Circularly Polarized FMCW Radar With a Single-Lens-Coupled SiGe HBT Chip

A complete circularly polarized 210–270-GHz frequency-modulated continuous-wave radar with a monostatic homodyne architecture is presented. It consists of a highly integrated radio-frequency transceiver module, an in-house developed linear-frequency chirp generator, and a data acquisition chain. The radar front end featuring a fundamentally operated $\times$ 16 multiplier-chain architecture is realized as a single chip in 0.13- $\mu$ m SiGe heterojunction bipolar transistor technology with a lens-coupled circularly polarized on-chip antenna and wire-bonded on a low-cost printed circuit board. In combination with a 9-mm-diameter silicon lens, the module achieves an average in-band directivity of 26.6 dB. The measured peak radiated power from the packaged radar module is $+$ 5 dBm and the noise figure is 21 dB. For a 60-GHz frequency sweep, the radar achieves a range resolution of 2.57 mm after calibration, which is close to the theoretical bandwidth-limited resolution of 2.5 mm. With a simple scanning optical setup, this paper further demonstrates the 3-D imaging capability of the radar for detection of hidden objects with a remarkable dynamic range of around 50 dB.

(Invited) SiGe BiCMOS for Optoelectronics

Silicon-based electronic-photonic integrated circuit (ePIC) technology enables a high degree of integration of optoelectronic sub-systems for optical communications. There are basically two approaches for merging photonics with electronics, hybrid assembly or monolithic integration. In hybrid integration approaches, electronic-only chips are combined with photonic-only chips after their separate fabrication [1]. Advantage is here that a mutual interference of photonic and electronic device fabrication can easily be avoided which is a more difficult task for most monolithic integration approaches. On the other hand, monolithic integration of photonic devices such as detectors and modulators in the frontend-of-line (FEOL) of a Si-based integrated circuit technology allows for shortest possible interconnects between photonics and electronics from which high-speed performance of electronic-photonic integrated circuits can greatly benefit. Moreover, monolithic electronic-photonic integration leads to shrinking form-factors and reduced assembly. Monolithic integration of Si photonics has been pursued for some time, chiefly on base of CMOS technologies [2, 3]. Looking beyond 100G systems, baud-rates exceeding 50GBd are needed for 400G transceivers, requiring very fast driving electronics. High-speed transistors are therefore a prerequisite for high-performance ePIC technology. Already today, SiGe bipolar or BiCMOS technologies are frequently deployed for broadband applications in high-speed discrete photonics. A key device figure of merit is the product of transit frequency and breakdown voltage (fT × BV) in which state-of-the-art SiGe heterojunction bipolar transistors (HBTs) outperform scaled MOS transistors. In result, SiGe HBTs are often preferred over CMOS for high-speed analog circuits. Although waveguide-based optics leads to lower form-factors compared to discrete solutions, there are limits to downsizing of integrated photonic devices because of the wavelength of light and the available index contrast. This puts constraints on the reduction of voltage swing required to drive photonic devices such as modulators. In practice, the required voltage swing remains comparable to discrete solutions. On the other hand, complex real-time mixed signal systems requiring large digital cores are typically implemented in highly scaled CMOS technologies that provide only a limited output voltage swing. Integrating Si photonics with SiGe HBT technology is therefore an excellent match for high-speed A/D or D/A interfaces. SiGe-HBT-based ePIC technology enables direct driving of integrated photonic devices by high-speed digital electronics such as advanced signal processing. Here, we will give an overview about IHP’s work in ePIC technology development under use of different SiGe BiCMOS baseline processes. Main focus is on “Photonic BiCMOS”, a new monolithic ePIC technology which combines high-performance BiCMOS technology with high-speed photonic devices for electronic-photonic sub-modules for next generation communication networks. We will describe the main features of this technology, including an overview of offered photonic and electronic devices. Examples of demonstrator circuits fabricated in a first generation of the new technology, comprising 200GHz SiGe HBTs and 30GHz Ge photodiodes, are also presented. Among these circuits are a 40Gbps monolithically integrated linear receiver [4] and a monolithically integrated segmented driver and Mach-Zehnder modulator with 13 dB extinction ratio at 28 Gbps [5]. We will also present our work to integrate a new Ge photodiode with 70GHz bandwidth and to improve the bipolar transistor performance to enable the fabrication of integrated receivers and transmitters with strongly increased optical line rates [6, 7]. In a second part of the talk we will demonstrate the potential of SiGe BiCMOS as the ‘electronics supplier’ for the hybrid integration approach, using IHP’s 0.13µm BiCMOS process SG13S offering HBTs with 240/320GHz fT/fmax. [1] F. Boeuf et al., “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s Applications,” in 2013 IEEE International Electron Devices Meeting (IEDM), pp. 353-356 [2] S. Assefa et al., “A 90nm CMOS integrated nano-photonics technology for 25Gbps WDM optical communications applications,” in 2012 IEEE International Electron Devices Meeting (IEDM), pp. 809-811 [3] R. Meade et al., “Integration of silicon photonics in bulk CMOS,” 2014 Symposium on VLSI Technology Digest of Technical Papers, DOI:10.1109/VLSIT.2014.6894427 [4] A. Awny et al., “A 40Gb/s monolithically integrated linear photonic receiver in a 0.25μm BiCMOS SiGe:C Technology,” IEEE Microwave and Wireless Components Letters, 25 (2015), 7, 469-471 [5] P. Rito et al., “A Monolithically Integrated Segmented Driver and Modulator in 0.25 μm SiGe:C BiCMOS with 13 dB Extinction Ratio at 28 Gb/s,” in press [6] D. Knoll et al., “High-performance photonic BiCMOS Process for the fabrication of high-bandwidth electronic-photonic integrated circuits,” in 2015 IEEE International Electron Devices Meeting (IEDM), pp. 402-405 [7] S. Lischke et al., “Photonic BiCMOS technology – Enabler for Si-based, monolithically integrated transceivers towards 400 G,” in press

A Comparison of the Degradation in RF Performance Due to Device Interconnects in Advanced SiGe HBT and CMOS Technologies

This paper investigates the impact of the interconnect between the bottom and the top metal layers on the transistor RF performance of CMOS and silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technologies. State-of-the-art 32-nm silicon-on-insulator (SOI) CMOS and 120-nm SiGe HBT technologies are analyzed in detail. Measured results indicate a significant reduction in the unity-gain frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) from the bottom to the top metal layer for advanced CMOS technology nodes, but only a slight reduction for SiGe HBTs. The 32-nm SOI CMOS and SiGe HBT technologies have a reduction in the maximum oscillation frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) from the bottom to the top metal layer of ~12% and 5%, respectively. By analyzing technology scaling trends, it is clear that SiGe HBTs can now achieve a similar peak f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> at the top metal layer in comparison with advanced CMOS technology nodes, and a significantly higher f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> . Furthermore, in CMOS technologies, the top metal layer f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> appears to have reached a peak around the 45-65-nm technology nodes, a result which has significant implications.

Large-Signal Reliability Analysis of SiGe HBT Cascode Driver Amplifiers

This paper presents the results of an investigation of the steady-state safe operating conditions for large-signal silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) circuits. By calculating capacitive currents within the intrinsic transistor, avalanche inducing currents through the transistor junctions are isolated and then compared with dc instability points established through simulation and measurement. In addition, calibrated technology computer-aided design simulations are used to provide further insight into the differences between RF and dc operation and stress conditions. The ability to swing the terminals of a SiGe HBT beyond the static $I$ – $V$ conditions coincident with catastrophic breakdown is explained. Furthermore, hot-carrier effects are also compared from multiple perspectives, with supporting data taken from fully realized $X$ -band and $C$ -band cascode driver amplifiers. This analysis provides microwave circuit designers with the framework necessary to better understand the full-voltage-swing potential of a given SiGe HBT technology and the resultant hot carrier damage under RF operation.

(Invited) Towards 0.7 Terahertz Silicon Germanium Heterojunction Bipolar Technology – The DOTSEVEN Project

DOTSEVEN is a very ambitious 3.5 year R&D project targeting the development of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) technologies with cut-off frequencies (fmax) of around 700 GHz. The project is publically funded within the European Union's Seventh Framework Program for Research (FP7). It started in October 2012 and is now at the beginning of its second year. 10 out of the 12 DOTSEVEN participants were already partnering in the predecessor FP7 project DOTFIVE which succeeded for the first time to push fmax of SiGe HBTs (at room temperature) into the 500 GHz region thus setting a new world-wide benchmark.For a given lithography node, SiGe HBTs provide much higher cut-off frequencies compared to CMOS transistors while offering higher power density and better analog performance. Although ITRS roadmaps [1] predict ever increasing cut-off frequencies for CMOS transistors up to the THz region, there are indications [2,3] that at least fmax will saturate around the 28 nm node at 300-400 GHz (depending on the extraction methodology) and will even drop beyond that node due to parasitic gate resistance [Figure 1]. Thus SiGe HBT technology and SiGe HBT enhanced CMOS (SiGe BiCMOS) will be key enablers for demanding mm-wave systems requiring more than a few µWatts of RF output power (which limits the applicability of even very advanced CMOS) and also offer high integration levels at low cost which precludes expensive and less integrated III-V solutions. Physics based simulations predict “balanced” fT/fmax limits of well above 1 THz for SiGe HBTs [4]. In DOTFIVE the practical performance limits of lateral and vertical scaling of standard HBT topologies which are in use in 200-300 GHz production processes at STM and IFX have shown up clearly. With these conventional DPSA (double poly self aligned) emitter / base structures incorporating an external poly-silicon base-contact which is vertically linked to the SEG (selectively grown) SiGe:C base layer, we were not able to surpass a “400 GHz” limit of fmax significantly [5]. Reaching 500 GHz was only possible with two new transistor architectures realized by IHP employing novel “lateral base-link” [6] or “epitaxial external base-contact” concepts [7] which will be utilized in DOTSEVEN as starting point as they have potential to overcome a basic weakness of conventional DPSA structures: their relatively high-resistive external base-link region [8,9].Within the project the capabilities and benefits of >500 GHz SiGe HBT technology will be demonstrated by benchmark circuits and advanced system applications in the 0.1 to 1 THz range like THz imaging and sensing, wireless Gb/s communications and millimeter-wave radar. Process development will be strongly supported by TCAD and physics-based modeling including 3D, nanoscale and thermal effects where as "first-time-right" circuit design will be enabled by accurate compact device modeling including electro-thermal, substrate and other parasitic effects. Of course these models have to be based on accurately extracted parameter sets for which in turn accurate and reliable characterization and extraction methodologies are mandatory. High current densities, excessive self-heating and operation at collector-emitter voltages above the open-base VCE breakdown limit might impose considerable reliability risks in downscaled HBTs and limit their practical application. Therefore in-depth reliability modeling and investigations will be undertaken in the project too.

Active 220- and 325-GHz Frequency Multiplier Chains in an SiGe HBT Technology

A 325-GHz ×18 frequency multiplier chain implemented in a fτ/fmax = 250 GHz/380 GHz evaluation SiGe heterojunction bipolar transistor technology is presented. The chain achieves a peak output power of -3 dBm and consists of a balanced doubler driven by two cascaded tripler stages. It operates from 317 to 328 GHz with a 0-dBm 18-GHz input signal and a 1.5-W power consumption. Additionally, 220- and 325-GHz doubler breakout circuits with integrated driver amplifiers are presented. The doublers reach an output power of -1 dBm at 220 GHz and -3 dBm at 325 GHz with a power dissipation of 630 and 420 mW, respectively.

High‐speed divide‐by‐4/5 prescalers with merged and gates using GaInP/GaAs HBT and SiGe HBT technologies

AbstractThis paper demonstrates the divide‐by‐4/5 prescalers with merged AND gates in 2‐μm GaInP/GaAs heterojunction bipolar transistor (HBT) and 0.35‐μm SiGe HBT technologies. By biasing the HBT near the peak transit‐time frequency (fT), the maximum operating frequency of a D‐type flip‐flop can be promoted. At the supply voltage of 5 V, the GaInP/GaAs prescaler operates from 30 MHz to 5.2 GHz, and the SiGe prescaler has the higher‐speed performance of 1–8 GHz at the cost of power consumption. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1498–1500, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23407

A Low-Power,$X$-Band SiGe HBT Low-Noise Amplifier for Near-Space Radar Applications

A low-power, X-band low-noise amplifier (LNA) is presented. Implemented with 180 GHz silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs), the circuit occupies 780times660 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The LNA exhibits a gain of 11.0 dB at 9.5 GHz, a mean noise figure of 2.78 dB across X-band, and an input third-order intercept point of -9.1 dBm near 9.5 GHz, while dissipating only 2.5 mW. The low-power performance of this LNA, together with its natural total-dose radiation immunity, demonstrates the potential of SiGe HBT technology for near-space radar applications

Review of SiGe HBTs on SOI

This paper reviews progress in SiGe Heterojunction Bipolar Transistors (HBT) on Silicon-On-Insulator (SOI) technology. SiGe HBTs on SOI are attractive for mixed signal radio frequency (RF) applications and have been of increasing research interest due to their compatibility with SOI CMOS (Complementary Metal Oxide Semiconductor) technology. In bipolar technology, the use of SOI substrate eliminates parasitic substrate transistors and associated latch-up, and has the ability to reduce crosstalk, particularly when combined with buried groundplanes (GP). Various technological SOI bipolar concepts are reviewed with special emphasis on the state-of-the-art SOI SiGe HBT devices in vertical and lateral design. More in depth results are shown from a UK consortium advanced RF platform technology, which includes SOI SiGe HBTs. Bonded wafer technology was developed to allow incorporation of buried silicide layers both above and below the buried oxide. New electrical and noise characterisation results pointed to reduced 1/ f noise in these devices compared to bulk counterparts. The lower noise is purported to arise from strain relief of the device structure due to the elasticity of the buried oxide layer during the high temperature epitaxial layer growth. The novel concept of the silicide SOI (SSOI) SiGe HBT technology developed for targeting a reduction in collector resistance, as well as for suppressing the crosstalk, is outlined. The buried tungsten silicide layers were found to have negligible impact on junction leakage. Further to vertical SiGe HBTs on SOI, the challenges of fabricating a lateral SOI SiGe HBT structure are presented.

Proton tolerance of fourth-generation 350 GHz UHV/CVD SiGe HBTs

We report, for the first time, the impact of proton irradiation on fourth-generation SiGe heterojunction bipolar transistors (HBTs) having a record peak unity gain cutoff frequency of 350 GHz. The implications of aggressive vertical scaling on the observed proton tolerance is investigated through comparisons of the pre-and post-radiation ac and dc figures-of-merit to observed results from prior SiGe HBT technology nodes irradiated under identical conditions. In addition, transistors of varying breakdown voltage are used to probe the differences in proton tolerance as a function of collector doping. Our findings indicate that SiGe HBTs continue to exhibit impressive total dose tolerance, even at unprecedented levels of vertical profile scaling and frequency response. Negligible total dose degradation in /spl beta/ (0.3%), f/sub T/ and f/sub max/(6%) are observed in the circuit bias regime, suggesting that SiGe HBT BiCMOS technology is potentially a formidable contender for high-performance space-borne applications.

Optimizing SiGe HBTs technology using small-signal and high frequency noise device's modeling

ABSTRACTThe rapid expansion of SiGe technologies during the last decade essentially due to civil telecommunication's applications have led Si/SiGe based heterojunction bipolar transistors (HBTs) to excellent performance levels, allowing high frequency low noise circuit designs such as linear low noise amplifiers( RF noise) or also low-phase noise oscillators (LF noise). Among these technologies, the SiGe BiCMOS one integrates digital and RF functions on the same chip. Fast improvements of the technological process have been performed thanks to large efforts allowed to characterization and modeling of the devices. We have investigated on the influence of technological parameters such as Germanium profile, doping level and thickness of the base layer (5 different wafers) on the dynamic and high frequency noise performances to converge towards the optimum technological process (now available with the BiCMOS6G processed by ST microelectronics). We made use of scattering parameters [S] measurements on the devices to extract the electrical parameters of our small signal model. The high frequency noise parameters based on the electrical model (with noise sources added to the junction, resistances) are simulated and compared with the measured noise parameters of the devices. The four noise parameters (Fmin, Rn, and complex Γopt) measurements have been performed from 1 GHz to 12 GHz, and the dynamic S parameters measurements have been realized in the 40 MHz-40 GHz range. These models have been used to enable the identification of the limiting parameters on the dynamic performances and on the high frequency noise parameters.

The effects of operating bias conditions on the proton tolerance of SiGe HBTs

The effects of operating bias conditions on the proton tolerance of Silicon–Germanium (SiGe) heterojunction bipolar transistors (HBTs) are investigated for the first time. While this SiGe HBT technology is relatively insensitive to different bias conditions during radiation exposure, the cases with all terminals grounded and with the emitter–base junction reverse-biased show slightly enhanced degradation at proton fluences above 2 × 10 13 p/cm 2 compared to the other bias configurations, consistent with 2D simulations, and can thus be viewed as worst case conditions.