SiGe Devices Research Articles

Evaluation of Anisotropic Biaxial Stress in Extremely-Thin Body (100) Silicon-Germanium-on-Insulator p-Type Metal-Oxide-Semiconductor Field-Effect-Transistor by Oil-Immersion Raman Spectroscopy

Background and ObjectiveSilicon germanium (SiGe)-on-insulator (SGOI) p-MOSFETs are expected for obtaining low power consumption and high current drive of CMOS since SiGe has higher hole career mobility than Si and the compressive strain can be induced in the SiGe channel without complicated heterostructures. In addition, the buried oxide between the Si substrate and the SiGe layer realizes suppression of leak current, and an extremely thin body (ETB) SGOI prevents short-channel effects. Strain engineering is important for improving the performance of p-MOSFETs because the hole mobility increases due to the compressive strain in the channel region. In previous studies, we have reported that anisotropic strain in ETB GOI channels of p-MOSFET improved electrical properties [1]. However, there are few reports regarding the detailed stress evaluation in ETB SGOI p-MOSFETs. The strain state has changed complicatedly by the SiGe device process. Therefore, a detailed stress measurement is indispensable to determine career mobility enhancement in the actual channel fabrication. In this study, we evaluated the anisotropic biaxial stress in the channel region of the ETB (100) SGOI p-MOSFETs by oil-immersion Raman spectroscopy.Experiments We prepared (100) SGOI p-MOSFETs along <110> with a channel thickness of approximately 10 nm by applying the Ge condensation process with slow cooling on the 60 nm-thick Si0.75Ge0.25 films epitaxially grown on SOI substrates with 10 nm-thick superficial Si layer [2]. We used the Ge condensation process that combined oxidation and intermixing annealing in order to suppress strain relaxation in the Ge-rich region [3] and obtained Ge-rich SiGe layer (Ge fraction: from 65 to 70%). For the evaluation of anisotropic biaxial stress in the SiGe channel region, we measured longitudinal optical (LO) and transverse optical (TO) phonon modes of Raman spectra for Ge-Ge vibration mode derived from SiGe by using oil-immersion Raman spectroscopy. In the oil-immersion Raman measurements, the wavelength of the excitation light source was 532 nm, the laser power at the sample surface was less than 1 mW, and the focal length of the spectrometer was 2,000 mm. The numerical aperture of the oil-immersion lens was 1.4, and the reflective index of oil was 1.5. We measured p-MOSFETs with different channel widths to examine the channel width dependence.Results and DiscussionFigure 1(a) and (b) show the Raman spectra of the LO and TO phonon modes obtained from the SiGe channel region at channel width (Wch) = 738 nm, respectively. We observed that Raman peaks of LO phonon mode shifted toward the higher wavenumber side compared to the Raman peak of strain-free SiGe. These results suggest that the high compressive strain is induced in the SiGe channel.Figure 1(c) shows the calculated transverse stress (σxx) and longitudinal stress (σyy) of the samples using LO and TO Raman shift for four different channel widths under the assumption of the anisotropic biaxial stress and Ge fraction 68% in the SiGe layer. From Fig. 1(c), we observed transverse stress (σxx) decreases with narrowing channel width. On the other hand, the longitudinal stress (σyy) did not significantly change regardless of channel width. These results suggest that the strain states in the SiGe channel region became closer to the uniaxial strain with narrowing the channel width. These changes are in good agreement with the previous electrical characteristics studies of the GOI p-MOSFETs [1], and it is expected that the compressive strain enhances the hole mobility in the ETB SGOI p-MOSFETs as well.AcknowledgementsThis work was supported by JSPS KAKENHI Grant Number 22H00208, Japan. A part of this work was conducted at Takeda Sentanchi Supercleanroom, The University of Tokyo, supported by "Nanotechnology Platform Program" of MEXT, Japan, Grant Number JPMXP09F-20-UT-0007. Reference [1] C. -T. Chen et al., IEEE Trans. Electron Devices 69, 1 (2022).[2] C. -T. Chen et al., Proc. IEEE Symp. VLSI Technology (2021).[3] K. -W. Jo et al., Appl. Phys. Lett. 114, 062101 (2019). Figure 1

Avalanche Modeling in Mextram 505 and Implications on Circuit Simulations

This paper presents recent advances in compact modeling of avalanche multiplication in Mextram 505, an industry-standard transistor model, including new model features, improved model implementations, and implications for SiGe HBT RF circuit simulation and device modeling.

High-temperature monolithic SiGe thermoelectric device directly heated by catalytic combustion

There has been a strong demand for portable power sources of mobile devices, which can substitute conventional lithium-ion batteries. In this study, a thermoelectric power generation device integrated with a catalytic combustor was developed in order to overcome limitations of previously proposed combustion-based system, such as low temperature difference and large heat loss. Monolithic SiGe thermoelectric generators (TEGs) with operating temperatures higher than 1100 °C were prepared, and Pd catalyst layers supported by porous alumina films were formed on the high-temperature end of the SiGe TEG device for direct heating obtained by catalytic combustion while minimizing the heat loss. A power generation test bench was developed with three SiGe devices. By using a butane/air mixture, the highest temperature and temperature difference over 1100 °C and 800 °C, respectively, were achieved without deterioration of the power generation performance.

Investigation of degradation behavior under negative bias temperature stress in Si/Si0.8Ge0.2 metal-oxide-semiconductor capacitors

In this paper, capacitance and conductance characteristics are used to explain reliability issues in metal-oxide-semiconductor capacitors (MOSCAPs) with a silicon-germanium (SiGe) channel. The SiGe channel devices are also comprehensively compared to traditional Si channel devices. After negative bias temperature stress, both exhibit flat-band voltage (V FB) shifts in the negative direction and a rise in the conductance hump. Generally, the process of Si devices is more stable than SiGe devices, resulting in the interface quality of Si MOSCAPs being better due to lattice constant matching at the interface. However, it is noteworthy that the degradation of Si MOSCAPs is more serious than that of Side MOSCAPs. Therefore, this study quantitatively extracts the interface defects and illustrates the generation of interface defects with a reaction-diffusion model. In addition, the difference in the injected energy level is used to explain the difference in the VFB shift.

Experimental investigation on the degradation of SiGe LNAs under different bias conditions induced by 3 MeV proton irradiation

The 3 MeV proton irradiation effects on SiGe low noise amplifier (LNA) (NXP BGU7005) performance under different voltage supply VCC (0 V, 2.5 V) conditions were firstly experimental studied in this present work. The S parameters including S11, S22, S21, 1 dB compression point and noise figure (NF) of the test samples under different bias voltage supply were measured and compared before and after 3 MeV proton irradiation. The total proton irradiation fluence was 1 × 1015 protons/cm2. The maximum degradation quantities of the gain S21 and NF of the test samples under zero bias are measured respectively 1.6 dB and 1.2 dB. Compared with the samples under 2.5 V bias supply, the maximum degradation of S21 and NF are respectively 1.1 dB and 0.8 dB in the whole frequency band. It is noteworthy that the gain and NF of SiGe LNAs under zero-bias mode suffer enhanced degradation compared with those under normal bias supply. The key influence factors are discussed based on the correlation of the SiGe device and the LNA circuit. Different process of the ionization damage and displacement damage under zero-bias and 2.5 V bias voltage supply contributed to the degradation difference. The underlying physical mechanisms are analyzed and investigated.

Operando study of the preferential growth of SiO2 during the dry thermal oxidation of Si0.60Ge0.40(001) by ambient pressure x-ray photoelectron spectroscopy

Controlling the grown oxide composition, the oxide/semiconductor interface properties, and the semiconductor surface composition is of interest for SiGe devices. We have used ambient-pressure x-ray photoelectron spectroscopy (AP-XPS) to study the initial stages of dry thermal oxidation of an epitaxial Si0.60Ge0.40(001) film on Si(001). Si 2p and Ge 3d chemical-state resolved AP-XPS was performed at 300 °C and O2 pressures (PO2) of 10−4, 10−2, and 1 mbar during oxide growth. The National Institute of Standards simulated electron spectra for surface analysis (SESSA) was used to analyze both the oxide composition and the thickness versus time for each pressure. At all three PO2, the SESSA analysis indicated that oxidation proceeds via three oxide growth rate regimes: an initial rapid regime, an intermediate transitionary regime, and finally a quasisaturation slow regime. The Si and Ge oxidation rates were found to be pressure dependent during the rapid regime with both rates decreasing monotonically with decreasing pressure. Results indicated that Ge was much more sensitive to changes in PO2 compared to Si. As a result, a decrease in PO2 resulted in significant suppression of GeO2 formation compared to SiO2. Using SESSA, we were able to quantify the grown oxide composition and the thickness, both of which were strongly dependent on O2 pressure. The Ge composition, in Si1−xGexO2, was found to decrease monotonically with decreasing PO2.

Baseband to 140-GHz SiGe HBT and 100-GHz InP DHBT Broadband Triple-Stacked Distributed Amplifiers With Active Bias Terminations

This article describes the design and performance of a 140-GHz SiGe and a 100-GHz InP triple-stacked HBT distributed amplifier with active bias terminations. The active bias network is configured to extend the practical low-frequency operation while maintaining gain flatness and linearity. Triple-stacked HBTs are used to increase the gain-bandwidth and linear output capability. The SiGe design is based on HBTs with a peak f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 300/350 GHz and achieves 11.7 dB of gain and a bandwidth from baseband to 140 GHz. The InP HBT design is based on DHBTs with a peak f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 250/250 GHz and obtains a gain of 10.8 dB and a bandwidth of 100 GHz. Although the SiGe design achieves 1.5 times higher gain-bandwidth, the InP DHBT design achieves ~3-4.5 dB greater IP3, P1 dB, and P3 dB while consuming only ~23% higher dc power. These results represent the first broadband performance comparison of near-identical (apples-apples) DA designs implemented in SiGe and InP HBT device technologies. Although there are previous reports of larger bandwidth distributed amplifiers in both InP and SiGe technologies demonstrated up through 200 GHz, the InP and SiGe monolithic microwave integrated circuits (MMICs) described in this article are believed to represent the highest bandwidths reported for HBT DAs using practical on-chip active bias terminations.

High mobility Si0.15Ge0.85 growth by using the molten target sputtering (MTS) within heteroepitaxy framework

High-speed SiGe film is promising use in photonics and electronics technologies continue to replace Si-based devices. High mobility Si0.15 Ge0.85 film on sapphire was grown at 890 °C substrate temperature by using a conventional magnetron sputtering system within the heteroepitaxy framework. 890 °C substrate temperate is impractical for commercial device manufacturing due to long thermal soak, loading time, and costly process. To leverage the practical SiGe device applications, the Molten Target Sputtering (MTS) techniques is developed. The MTS is an economic and robust process from high flux density and liquid-state of molecules benefits. At 500 °C, the lowest substrate temperature, high mobility Si0.15Ge0.85 film with continues morphology and 99.7% majority-orientation were grown by using the MTS. The hall electron mobilities of the Si0.15Ge0.85 grown at 500 °C are 456 cm2V−1s−1 and 123.9 cm2V−1s−1 at 5.59 × 1018 cm3 and 3.5 × 1020 cm3 carrier concentration at 22.38 °C, respectively. The values are 550% higher hall electron mobilities than that of Si at equivalent carrier concentration and temperatures. We envision that the MTS is beneficial for the heteroepitaxy framework film growth that requires high substrate temperature to overcome the large lattice parameter mismatch between film and substrate.

An approach for determining thermal resistance model parameters of SiGe HBT

AbstractThis paper presents an improved method for determining the thermal resistance and junction temperature for silicon germanium heterojunction bipolar transistors. This method is a full analytical procedure without any iteration based on a set of accurate expressions. The thermal resistance is tested against iterative and analytic methods reported before. Good agreement is obtained between simulated and measured results for three SiGe devices with different emitter geometries.

Effect of Si/Sige Buried Gate with Strained Layers on N-Type Channel Properties

As the scaling down limit is approaching, the effect of structural and material specific limitations on the device characteristics was significantly increased. In terms of structure, formation of parasitic capacitors in the word line must be restricted in order to secure the sensing margin of the DRAM and the channel length must be secured for effective channel control. The buried gate is currently being applied in these two aspects. In terms of channel materials, as one of the possible candidates for mass-production, it is permissible to form strained silicon on the fully relaxed SiGe layer to improve the electron mobility. However, when growing SiGe without gradually increasing the concentration of Ge on Silicon substrate, the threading dislocation occur due to the lattice mismatch between the silicon substrate and silicon germanium layer. In this study, the process were investigated to form defect free and fully relaxed SiGe layer on silicon substrates by using hydrogen implantation and then growing strained silicon on the SiGe layer. The buried gate formed from the strained silicon surface to the top of the relaxed silicon germanium layer and the effect of strained Si and SiGe n-type channel characteristics on the device was investigated. We present a review on defect-free SiGe layer formation and device characteristics including the electron mobility of the strained Si/SiGe buried gate.

A 12-bit 1.0/2.0 GS/s Pipeline ADC in 0.18 µm SiGe BiCMOS

ABSTRACTA 12-bit time-interleaved 1.0/2.0 GS/s pipeline analogue–digital converter (ADC) is presented and implemented in 0.18 µm SiGe BiCMOS. Such an ADC consists of two identical channels, each of which can operate at 1 GS/s. The two same channels can be interleaved to achieve 2 GS/s speed. In one-channel ADC, four lanes of pipeline ADCs with 250 MS/s are interleaved to realise 1 GHz conversion. To avoid the timing skew-induced error among the four lanes, a dedicated T/H is adopted in one channel. A clock buffer with low jitter is presented to provide a low-voltage swing clock for the T/H by using SiGe devices. The proposed timing system generates the phases needed accurately. A single reference buffer is employed in one-channel ADC to avoid the gain mismatches among the four lanes. An analogue mux with the proposed switch chooses the mode of interleaving or non-interleaving. A trimming digital–analogue converter is employed to eliminate the gain mismatches between the two channels. The measured SNDR and SFDR for one-channel ADC @ 1 GS/s are 60 and 76 dB with Nyquist input. For the interleaved two channels @ 2 GS/s, SNDR and SFDR can achieve 58 and 61 dB with Nyquist input.

Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET

In this work, we have studied gate length (Lgate) scalability of Si0.55Ge0.45 Implant Free Quantum Well (IFQW) pFET with raised and embedded Si0.75Ge0.25 source/drain structures. Although embedded SiGe device shows higher Idsat which can be attributed to thinner Tinv (more scavenging of High-k interfacial layer), raised SiGe device has better short channel control than embedded SiGe device thanks to shallower junction depth. Raised SiGe device can scale down Lgate by 4 nm compared to embedded SiGe device while maintaining identical Ioff. This results in superior intrinsic delay in raised SiGe device.

Material lattice orientation effect of local Si1-xGex stressors on the width dependence of high-k metal gate PMOSFETs

The novel material selection and fabrication became a major concern due to scaling limitations when the technology node was below 20 nm. Complex gate-last process step for high-k metal gate (HKMG) device was proposed to enhance device mobility gain through the proper assistance of boosting channel stress. However, the impact of anisotropic material behavior regarding SiGe and silicon device is rarely estimated. Thus, the foregoing mechanical responses combined with concerned device layout during gate etch, replacement metal gate must be investigated. In this study, a process-oriented simulation methodology was presented to investigate this critical issue by a vehicle of 20 nm short-channel HKMG p-type MOSFET with embedded SiGe alloy stressor. Results indicated that the poly gate etch process significantly improved the longitudinal channel stress (Sxx) of this device channel. Process-induced Sxx values of −306.94 and −1325.48 MPa were obtained when the gate-first and gate-last processes were estimated, and 100 nm gate width was achieved, respectively. Given the increase in gate widths from 100 nm to 4000 nm, the maximum carrier mobility of 116.57% and 111.01% were obtained when isotropic and anisotropic material properties were adopted.

Border traps and bias-temperature instabilities in MOS devices

An overview of the effects of border traps on device performance and reliability is presented for Si, Ge, SiGe, InGaAs, SiC, GaN, and carbon-based MOS devices that are subjected to bias-temperature stress, with or without exposure to ionizing radiation. Effective border-trap densities and/or energy distributions are estimated using capacitance-voltage hysteresis, low-frequency noise, charge pumping, and other electrical techniques that vary the time scale over which charge exchange between the semiconductor channel and near-interfacial dielectric. Oxygen vacancies and hydrogen impurity complexes are common border traps in a wide variety of systems subjected to bias-temperature stress. Charge trapping and emission tend to dominate observed bias-temperature instabilities for as-processed devices at higher oxide electric fields (>4–6MV/cm), and for irradiated devices. Hydrogen diffusion and reactions become relatively more significant in as-processed devices at lower electric fields (<4–6MV/cm).

The Impact of Dummy Gate Processing on Si-Cap-Free SiGe Passivation: A Physical Characterization Study on Strained SiGe 25% and 45%

High mobility channel materials like SiGe, Ge and IIIV receive lots of interest in order to enable the continuation of Moore’s path during the upcoming technology nodes. Recently Si-cap-free SiGe passivation with the number of interface states (NIT) down to 2 1011 cm-2 have been demonstrated. [1-3] A clear correlation was established between Ge-content in the SiGe-oxide and NIT. Unfortunately no process information has been provided on how the Ge-oxide-free interlayers were obtained. In a separate study the impact of HF, HCl and SC1 cleaning solution on the SiGe surface and oxide composition was reported. [4] A comparison of SiGe Gate-All-Around (GAA) and FinFET devices using a Si-cap-free SiGe 25% passivation scheme in a replacement metal gate (RMG) integration indicate the device performance is improved by a TMAH (aq) treatment prior to SiGe interlayer formation and high-k deposition. [5] Here the formation of a SiGe wet chemical oxide will be presented. The impact of dummy gate processing on the interlayer composition is reported. Also the impact of a TMAH (aq) treatment prior to chemical oxide formation has been analyzed and will be reported. Blanket strained SiGe 25% and 45% were grown by epitaxy. The SiGe-substrate and -oxide composition were measured by angle-resolved XPS using the Si2p and Ge3d peaks. The Ge3d peak is fitted with three different compounds: elemental Ge, GeO2 and Ge-suboxide. The angle dependence lets us estimate the distribution of the different components with respect to the sample top surface. An concentration increase with increasing angle (relative to the surface normal) indicates the compound is located closer to the sample surface. And reversely a concentration increase with increasing angle indicates the compound is located deeper into the sample. A native oxide was grown on SiGe 25 and 45% by exposing the wafers to the cleanroom air for approx. 1 week. The native oxide was found to be stoichiometric or nearly stoichiometric with a uniform Ge content throughout the oxide for SiGe 25 and 45% respectively. A wet chemical oxide was grown using an ‘imec clean’ [6] having a final O3/HCl (aq) rinse. The wet chemical oxide is Ge-poor compared to the SiGe substrate. No or only a small variation in Ge content of the SiGe-oxide is seen with ARXPS. However the fraction Ge-suboxide decreases with increasing angle, indicating the Ge-suboxide are located deeper within the sample, so closer to the SiGe-oxide/SiGe-substrate interface. The Ge-content of the SiGe-substrate after wet chemical oxidation shows a weak incident-angle-dependence, indicative a limited Ge enrichment of the SiGe substrate towards the SiGe-oxide/-substrate interface. The low Ge content of the SiGe-oxide is attributed to the water solubility of GeO2. The increase in Ge-content towards the SiGe-oxide/-substrate can be (at least partially) attributed to the poor water solubility of Ge-suboxide. The small increase in Ge content of the SiGe substrate can be attributed to the thermodynamically preferred oxidation of Si over Ge. The combined impact of dummy gate deposition, spike anneal and dummy gate removal prior to SiGe interlayer formation was investigated by AR-XPS and SIMS. The temperature used during spike anneal was found to have a significant impact on the Ge-content of the SiGe-oxide formed during an O3-last imec clean. The results will be reported in detail at the conference. The impact of TMAH (aq) on the chemical oxide composition and surface roughness will also be reported. TMAH (aq) was found to improve SiGe device performance. [5] Also the interaction with the subsequent HfO2 deposition will be reported. In summary SiGe is found to behave as a non-linear combination of Si and Ge. In HF-free aqueous solutions, the SiGe oxide composition is a combination of (1) thermodynamically preferred oxidation of Si versus Ge; (2) poor water-solubility of SiO2 and/or its low solubilization rate; and (3) fast dissolution of GeO2 but slow dissolution of Ge-suboxides. [1] CH Lee et al. VLSI 2016. [2] S. Siddiqui et al. presented MRS Spring Meeting 2016. [3] CH Lee et al. IEDM 2016. [4] S.L. Heslop et al. ECS Trans 69 (2015) 287. [5] H. Mertens et al VLSI 2015. [6] M. Meuris et al. Solid State Phenom, July 1995, p. 109. Figure 1

Superior NBTI in High- $k$ SiGe Transistors–Part I: Experimental

SiGe quantum-well pMOSFETs have recently been introduced for enhanced performance of transistors. Quite surprisingly, a significant reduction in negative bias temperature instability (NBTI) was also found in these devices. Furthermore, a stronger oxide field acceleration of the degradation in SiGe devices compared with Si devices was reported. These observations were speculated to be a consequence of the energetical realignment of the SiGe channel with respect to the dielectric stack. As these observations were made on large-area devices, only the average contribution of many defects to NBTI could be studied. In order to reveal the microscopic reasons responsible for the improved reliability, a detailed study of single defects is performed in nanoscale devices. To provide a detailed picture of single charge trapping, the step-height distributions for different device variants are measured and found to follow a unimodal and bimodal distribution. This finding suggests two conducting channels, one in the SiGe and one in the thin Si cap layer. We, furthermore, demonstrate that similar trap depth distributions are present among the device variants supported by a similar stress bias dependence of the capture times of the identified single defects. We conclude that NBTI is primarily determined by the dielectric stack and not by the device technology.

(Invited) Bringing III-Vs into CMOS: From Materials to Circuits

High-mobility channel materials such as InGaAs and SiGe alloys are considered to be the leading candidates for replacing strained Si in future low power/high performance logic circuits. However, the integration of InGaAs on Si and the co-integration of InGaAs devices with SiGe devices are extremely challenging. On the one hand, the large lattice mismatch (8 to 10%) and the potential formation of antiphase domains at the polar/non-polar III-V/Si crystalline interface typically hinder the integration of high quality InGaAs crystals on Si. On the other hand, InGaAs and SiGe require very different processing conditions in terms of thermal budgets, dry and wet chemistries, passivation schemes and contacting schemes which complexifies the realization of CMOS circuits. Recently, tremendous progress were achieved as a result of innovation at the material and device levels. Latest technology developments yielded the first demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si, fabricated with InGaAs selective epitaxy and standard front end of line processes in a 2D co-planar configuration. This novel and scalable CMOS integration scheme enables InGaAs nFET fabrication in close proximity to SiGe pFETs (down to 25 nm spacing), resulting in 6T-SRAM arrays having a minimum cell size below 0.45 μm2. This scheme can be combined with any bulk Si or SOI-based planar or fin technology, and is compatible with standard large-area Si substrate. Furthermore, progress on 3D Monolithic integration showed that this integration scheme not only an opportunity for further density scaling, but it also offers unique advantages for solving the integration of high mobility materials for 3D CMOS and stacking of functional layers on top of standard CMOS circuitry.

Wavelength conversion of complex modulation formats in a compact SiGe waveguide

We report a nonlinear signal processing system based on a SiGe waveguide suitable for high spectral efficiency data signals. Four-wave-mixing (FWM)-based wavelength conversion of 10-Gbaud 16-Quadrature amplitude modulated (QAM) and 64-QAM signals is demonstrated with less than -10-dB conversion efficiency (CE), 36-dB idler optical signal-to-noise ratio (OSNR), negligible bit error ratio (BER) penalty and a 3-dB conversion bandwidth exceeding 30nm. The SiGe device was CW-pumped and operated in a passive scheme without giving rise to any two-photon absorption (TPA) effects.

Challenges and Opportunities of Near and Mid-Infrared Photonics Based on SiGe and Ge

Silicon-germanium (SiGe) and germanium (Ge) have been investigated as high-mobility channel materials for high-performance metal-oxide-semiconductor field-effect transistors (MOSFETs). The intense development of heterogeneous integration of SiGe and Ge on Si has given us opportunities to integrate new functionalities on Si platform. Since SiGe and Ge have narrow bandgap energies which match to photon energies used in optical fiber communication, SiGe/Ge photodetectors monolithically integrated on Si are available, evoking the emergence of Si photonics technology as a standard photonics integrated circuit (PIC) platform. In addition to photodetector (PD) applications, we have investigated the heterogeneous integration of SiGe and Ge on Si to extend the functionalities for Si photonics platform. In this paper, we present challenges and opportunities of SiG and Ge for near and mid-infrared integrated photonics. We have investigated strained SiGe to enhance the modulation efficiency of Si-based optical modulators. Since there are no significant electro-optic effects in Si, free-carrier modulation is a common method to modulate optical properties such as refractive index and absorption coefficient. However, the weak free-carrier effects such as the plasma dispersion effect and free-carrier absorption result in low modulation efficiency. To cover the shortcoming of Si, we have proposed to introduce strained SiGe. We have predicted that biaxial compressive strain enhances the free-carrier effect because of the light hole effective mass in SiGe [1]. Owing to the lattice-mismatch between Ge and Si, biaxial compressive strain is introduced into SiGe grown on Si. According to the Drude model, we have estimated approximately three times greater plasma dispersion effect in SiGe than in Si when a Ge content in SiGe is 0.5. To demonstrate the enhanced free-carrier effects in SiGe, carrier-injection SiGe optical modulators have been explored. First we have examined the free-carrier absorption by measuring the optical attenuation in the SiGe modulator with varied injection current. We have observed approximately two times greater absorption in the SiGe device than in the Si device [2]. We have also fabricated a SiGe Mach-Zehnder interferometer (MZI) optical modulator to evaluate refractive index change precisely. The enhanced plasma dispersion effect in SiGe have bee also confirmed [3], proving the concept of the strain-induced enhancement in the free-carrier effect. We have also investigated SiGe optical modulators based on accumulation [4] and depletion [5]. Thus, strained SiGe is also very promising for optical modulator applications as well as transistor application. We have also investigated Ge-based photonics by using CMOS compatible process technologies. First we have examined the surface passivation impact on the dark current of Ge PDs. Owing to the high-quality Ge oxide/Ge interface, we have achieved extremely low dark current density of 0.032 mA/cm2 in conjunction with the gas phase doped n+/p junction [6]. We have also revealed the impact of fixed charged in the passivation layer on the dark current [7]. Since Ge is transparent in mid-infrared wavelengths, Ge photonics is emerging as mid-infrared integrated photonic platform for bio/medical and environmental sensor applications. We have proposed the Ge CMOS photonics platform by using a Ge-on-insulator (GeOI) wafer [8]. We have fabricated a high-quality GeOI wafer by wafer bonding. Ge waveguide devices including rib waveguides, bend waveguides, MMI couplers, ring resonators, optical modulators have been successfully demonstrated on the GeOI wafer [9, 10]. In conclusion, the heterogeneous integration of SiGe and Ge on Si opens up many possibilities for optoelectronic application for near and mid-infrared wavelengths as well as electronics applications. This work was supported by a Grant-in-Aid for Young Scientists (S) from MEXT, and NEDO “PECST” project.

In-Line Critical Dimension and Sidewall Roughness Metrology Study for Compound Nanostructure Process Control by in-Line 3D Atomic Force Microscope

Critical dimension control is a key quality factor for better semiconductor device performance and yield and it is even more critical in 5 nm technology node beyond Si and SiGe device, where very high-mobility channel or new devices based on III-V and Ge, like directed self-assembled vertical nanowires, and tunnel FETs. Several in-line metrology techniques such as CD-SEM and scatterometry (or OCD) show a strong value in CD, LER, LWR, pitch and height monitoring in terms of throughput. The optical metrology technique especially OCD is sensitive to the refractive index, n and extinction coefficient, k of film on the structure. Thus it is hard to develop robust OCD library for III-V compound nanostructure due to change of n and k values as composition variation. Thus, it requires an unique in-line metrology technique that is less sensitive to material properties for robust process monitoring and yield control. In addition, as the drive current in a FinFET device flows along the vertical sidewalls, the surface quality of the sidewall strongly influences carrier mobility and device lifetime, leakage current so on and rough sidewall makes them worse. Sidewall roughness characterization, thus, become a critical issue and it needs to be controlled and monitored during process. However, in-line metrology technique could not been introduced for monitoring the quality of sidewall roughness yet. In this study, in-line 3 dimension atomic force microscopy (3D-AFM) was investigated to measure critical dimension parameters as complementary solution to the current in-line metrology tool sets and to develop fab compatible and high throughput in-line sidewall roughness monitoring solution. 3D-AFM (or CD-AFM) is used to consider as a reference tool for CD calibration in the ITRS roadmap because of high accuracy and atomic resolution without sample damage during measurement, but it is very slow. Therefore, we focus on not only measurement technique itself for compound nanostructure, but also how to implement the technique into the operation from process control perspective. Si, SiGe and InGaAs/InP fins with various pitch were used and their CD, height and sidewall roughness were measured by in-line 3D-AFM (NX-3DM, Park Systems). The system consists of XY and Z scanners independently, which allows the Z scanner head to tilt by 0, 19˚ and 38˚ depending on pattern dimension. Measurement In order to measure fin with the pitch of 45 nm, e-beam deposited amorphous carbon fiber with the diameter of 10 nm and the height of 150 nm (M-CNT-150, Nanotools) was used. In order to evaluate fab operation capabilities such as mapping capabilities, probe to probe reliability and long term reliability of tool, recipes with 27 die map were developed. In order to verify the measurement accuracy TEM verification was performed. Critical dimension of Si, SiGe and InGaAs/InP fins were successfully measured and especially CD and height of Si and SiGe fin with 45 nm pitch were measured successfully with CNT probe and all measured parameters were verified by TEM and it showed all good agreement. It means that CD and height information with material insensitive could be done by in-line 3D-AFM. Long term reliability was also evaluated and it showed that its 3σ value was 0.6 nm and peak to valley of the value was less than 1 nm. We think that non-contact measurement technique allows to reach this good repeatability. In-line 3D-AFM could successfully measure and differentiate between sidewall roughness of Si and InGaAs/InP nanostructures, which were treated at different process. Tilt angle influence was evaluated and different tilt angle did not influence roughness value and its resolution. Roughness value at different space was measured and it shows similar sidewall roughness. Probe to probe repeatability was checked and it shows good long term reliability and repeatability of the in-line 3D AFM system. In-line 3D AFM successfully measured critical dimension and sidewall roughness of Si, SiGe and InGaAs/InP nanostructure in atomic scale with good reliability. AFM with tilt head allows AFM probe to access pattern sidewall. As a result in-line 3D AFM could be used as a process monitoring for next generation device fabrication process such as III-V FinFET and GAA FET. In-line 3D-AFM could be used as complementary solution to other in-line metrology tools. Hybridization of in-line 3D-AFM with CD-SEM and OCD could make metrology system more accurate and learning cycle and recipe development faster.