Effect of Si/Sige Buried Gate with Strained Layers on N-Type Channel Properties

Abstract

As the scaling down limit is approaching, the effect of structural and material specific limitations on the device characteristics was significantly increased. In terms of structure, formation of parasitic capacitors in the word line must be restricted in order to secure the sensing margin of the DRAM and the channel length must be secured for effective channel control. The buried gate is currently being applied in these two aspects. In terms of channel materials, as one of the possible candidates for mass-production, it is permissible to form strained silicon on the fully relaxed SiGe layer to improve the electron mobility. However, when growing SiGe without gradually increasing the concentration of Ge on Silicon substrate, the threading dislocation occur due to the lattice mismatch between the silicon substrate and silicon germanium layer. In this study, the process were investigated to form defect free and fully relaxed SiGe layer on silicon substrates by using hydrogen implantation and then growing strained silicon on the SiGe layer. The buried gate formed from the strained silicon surface to the top of the relaxed silicon germanium layer and the effect of strained Si and SiGe n-type channel characteristics on the device was investigated. We present a review on defect-free SiGe layer formation and device characteristics including the electron mobility of the strained Si/SiGe buried gate.