Sidewall Scallops Research Articles

Selective MOCVD synthesis of VO2 crystals on nanosharp Si structures

High-quality single VO2 nanocrystals and ordered arrays of VO2 nanorings were selectively synthesized by chemical vapor deposition (CVD) respectively on the tip apices and on the sidewall scallops.

Comparative evaluations on scallop-induced electric-thermo-mechanical reliability of through-silicon-vias

Sidewall scallops of through-silicon-vias (TSVs) formed during the Bosch etching process will bring serious challenges to TSV reliability. In this paper, the impact of sidewall scallops on the electric-thermo-mechanical reliability of TSVs is investigated, where the self-heating effect of TSV conductor and the residual stress caused by the deposition of different TSV layers are involved. Utilizing multi-physics field analysis with sub-modeling technique, the electric-thermo-mechanical reliability of TSVs is assessed by different indicators, including current density, temperature, heat flux and von Mises stress. It is shown that, the presence of sidewall scallops will result in periodic fluctuations in terms of current density, heat flux and stress distributions, which will further undermine TSV reliability. However, the comparative study between TSVs with polyimide liner and conventional SiO2 liner demonstrates that, employing polyimide as TSV liner can eliminate various scallop-induced fluctuations and improve the electric-thermo-mechanical reliability of TSVs effectively.

Elimination of Scallop-Induced Stress Fluctuation on Through-Silicon-Vias (TSVs) by Employing Polyimide Liner

3-D modeling of through-silicon-via (TSV) with sidewall scallops, combined with an element birth and death technique, is explored in finite-element analysis (FEA) in this paper to evaluate and improve the thermo-mechanical reliability. Compared with the classic FEA, the proposed modeling and simulation method takes into account the process sequence and, hence, can accurately characterize the stress distribution and fluctuation phenomenon of TSVs, which agrees pretty well with X-ray experimental data. In order to solve the stress fluctuation problem, the process-friendly polyimide dielectric liner is employed to replace the SiO2 liner, which smoothens the sidewalls, reduces the average stress values, and eliminates the local stress fluctuation. The average stress on TSVs with a polyimide liner along the silicon-liner interface and copper-barrier interface are both lower than TSVs with an SiO2 liner and the fluctuation magnitude is also dramatically decreased, which demonstrates that the TSV with a polyimide liner has higher reliability and lower risks in interfacial delamination. Furthermore, the keep-out zone size is also decreased by using a polyimide liner, which is beneficial to realize high-density 3-D integration.

Stress Considerations for System-on-Chip Gas Sensor Integration in CMOS Technology

For several decades, researchers have aspired to combine all of the necessary components for a gas sensor with microelectronic circuits in order to create an integrated smart gas sensor device. However, these devices will only be embraced by industry and consumers if their cost of production is reduced to about $1 per device. The drive for affordable processing, integrable in complementary metal-oxide semiconductor technology, has lead to the implementation of novel techniques for the deposition of the sensing metal oxide layer and the use of 3D integration with through-silicon vias (TSVs). This paper analyzes, by means of modeling and simulation, the stress generation due to this integration, including the effects of TSV etching and metal-oxide deposition on the stress development in the devices’ conducting layers and in the surrounding silicon. Two types of TSVs are investigated: a filled copper TSV and one with an open cavity and tungsten-lined sidewalls. The influence of sidewall scallops, present as a result of the deep reactive ion etching process, on the build-up of stress in the region is also analyzed. The thermal stress resulting from the spray pyrolysis deposition of the metal-oxide sensing layer, performed at 400 °C, is investigated along with the intrinsic stress which builds up during metal growth described with the Volmer-Weber model.

Fabrication of high aspect ratio structure and its releasing for silicon on insulator MEMS/MOEMS device application

We systematically investigate the fabrication and dry-release technology for a high aspect ratio (HAR) structure with vertical and smooth silicon etching sidewalls. One-hundred-micrometer silicon on insulator (SOI) wafers are used in this work. By optimizing the process parameters of inductively coupled plasma deep reactive-ion etching, a HAR (∼25∶1) structure with a microtrench width of 4 μm has been demonstrated. A perfect etching profile has been obtained in which the structures present an almost perfect verticality of 0.10 μm and no sidewall scallops. The root-mean square roughness of silicon sidewalls is 20 to 29 nm. An in situ dry-release method using notching effect is employed after etching. By analysis, we found that the final notch length is typically an aspect-ratio-dependent process. The structure designed in this work has been successfully released by this in situ dry-release method, and the released bottom roughness effectively prohibits the stiction mechanism. The results demonstrate potential applications for design and fabrication of HAR SOI MEMS/MOEMS.

Influence of Bosch Etch Process on Electrical Isolation of TSV Structures

Bosch process is widely used in the fabrication of through silicon via (TSV) holes for 3-D integrated circuit and 3-D Packaging applications mainly due to its high silicon etch rate and selectivity to mask. However, the adverse impact on the electrical performance of the TSV due to the sidewall scallops or wavy profile due to the cyclical nature of the Bosch process has not been thoroughly investigated. This paper therefore focuses on the impact of sidewall scallops on the inter-via electrical leakage performance. Based on finite element analysis, this paper describes that the high stress concentration on the dielectric and barrier layers at the sharp scallops can potentially contribute to barrier failure. It is demonstrated that by smoothening the sidewalls of the TSV, the thermo-mechanical stresses on the dielectric and tantalum barrier is significantly reduced. A test vehicle is designed and fabricated with different geometry of deep silicon vias to study the impact of sidewall profile smoothening for different copper diffusion barrier stacks. It is experimentally demonstrated that the inter-via electrical leakage current can be reduced by almost three orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall. It is also indicated that it is sufficient to smoothen the initial few micrometers of the TSV depth by using a non-Bosch etch process. It is concluded that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, by tailoring a short initial etch step to smoothen the top sidewalls to minimize the adverse effects of the sidewall scallops.

Fabrication of Novel High Aspect Ratio Pillars using Fine Flexible mold by UV-NIL

abrication of novel high aspect ratio pillars like Gecko's foot-hairs has been demonstrated by UV nanoimprint lithography using PDMS Template. Si master mold having scalloped structures is prepared by deep Si etching process and the pattern is transferred to PMDS template. The pattern is again transferred to UV resist by UV nanoimprint using replicated PDMS template. Using PDMS template, high aspect ratio pillars with side wall scallops were successfully replicated.

Fabrication and demonstration of square lattice two-dimensional rod-type photonic bandgap crystal optical intersections

This paper reports fabrication and demonstration of optical intersections in two-dimensional (2D) rod-type photonic crystal (PhC) structures. High resolution and aspect ratio 2D square lattice PhC waveguide intersections were designed and fabricated for application at the optical communication wavelengths centered at 1550 nm. In the silicon processing front, challenges resolved to overcome issues of drastically reduced process windows caused by the dense PhC rods arrays with critical dimensions (CDs) reduced to only a few hundred nanometers were addressed not only in terms of critical process flow design but also in the development of each processing module. In the lithographic process of deep ultraviolet laser system working at 248 nm, PhC rods of sub-lithographic wavelength CDs (115 nm in radii) were realized in high resolution, even near periphery regions where proximity errors were prone. In the deep etching module, stringent requirements on etch angle control and low sidewall scallops (undulations arising from time multiplexed etch and passivation actions) were satisfied, to prevent catastrophic etch failures, and enable optical quality facets. The successfully fabricated PhCs were also monolithically integrated with large scale optical testing fiber grooves that enabled macro optical fiber assisted coupling to the micro scale PhC devices. In the optical experiments, the transmission and crosstalk properties for the PhC intersection devices with different rod radii at the center of the PhC optical waveguides crossings were measured with repeatability. The properties of the PhC intersections were therefore optimized and verified to correspond well with first principle finite difference time domain simulations.

Simulation of the Bosch process with a string–cell hybrid method

This paper presents a new two-dimensional (2D) simulator, which can simulate the etching polymerization alternation in the Bosch process for an infinite trench. Physical models for etching and deposition are developed. Having been implemented with these models and a string–cell hybrid method based on string structure and cell structure, this simulator has the ability to simulate the etching of different material types. After model parameter extraction from experiments, this simulator is used to simulate several phenomena in the Bosch process, including the formation and adjustment of sidewall scallops and the profile control of trench etching. The simulation results are compared with experiments and a good match can be found.