Stress Considerations for System-on-Chip Gas Sensor Integration in CMOS Technology

Abstract

For several decades, researchers have aspired to combine all of the necessary components for a gas sensor with microelectronic circuits in order to create an integrated smart gas sensor device. However, these devices will only be embraced by industry and consumers if their cost of production is reduced to about $1 per device. The drive for affordable processing, integrable in complementary metal-oxide semiconductor technology, has lead to the implementation of novel techniques for the deposition of the sensing metal oxide layer and the use of 3D integration with through-silicon vias (TSVs). This paper analyzes, by means of modeling and simulation, the stress generation due to this integration, including the effects of TSV etching and metal-oxide deposition on the stress development in the devices’ conducting layers and in the surrounding silicon. Two types of TSVs are investigated: a filled copper TSV and one with an open cavity and tungsten-lined sidewalls. The influence of sidewall scallops, present as a result of the deep reactive ion etching process, on the build-up of stress in the region is also analyzed. The thermal stress resulting from the spray pyrolysis deposition of the metal-oxide sensing layer, performed at 400 °C, is investigated along with the intrinsic stress which builds up during metal growth described with the Volmer-Weber model.