Sidewall Profile Research Articles

Nanofabrication and characterization of high-line-density x-ray transmission gratings

We report the nanofabrication and characterization of x-ray transmission gratings with a high aspect ratio and a feature size of down to 65 nm. Two nanofabrication methods, the combination of electron beam and optical lithography and the combination of electron beam, x-ray, and optical lithography, are presented in detail. In the former approach, the proximity effect of electron beam lithography based on a thin membrane of low-z material was investigated, and the x-ray transmission gratings with a line density of up to 6666 lines/mm were demonstrated. In the latter approach, which is suitable for low volume production, we investigated the x-ray mask pattern correction during the electron beam lithography process and the diffraction effect between the mask and wafer during the x-ray lithography process, and we demonstrated the precise control ability of line width and vertical side-wall profile. A large number of x-ray transmission gratings with a line density of 5000 lines/mm and Au absorber thickness of up to 580 nm were fabricated. The optical characterization results of the fabricated x-ray transmission gratings were given, suggesting that these two reliable approaches also promote the development of x-ray diffractive optical elements.

Deep reactive ion etching of 4H-SiC via cyclic SF6/O2 segments

Cycles of inductively coupled SF6/O2 plasma with low (9%) and high (90%) oxygen content etch segments are used to produce up to 46.6 µm-deep trenches with 5.5 µm-wide openings in single-crystalline 4H-SiC substrates. The low oxygen content segment serves to etch deep in SiC whereas the high oxygen content segment serves to etch SiC at a slower rate, targeting carbon-rich residues on the surface as the combination of carbon-rich and fluorinated residues impact sidewall profile. The cycles work in concert to etch past 30 µm at an etch rate of ~0.26 µm min−1 near room temperature, while maintaining close to vertical sidewalls, high aspect ratio, and high mask selectivity. In addition, power ramps during the low oxygen content segment is used to produce a 1:1 ratio of mask opening to trench bottom width. The effect of process parameters such as cycle time and backside substrate cooling on etch depth and micromasking of the electroplated nickel etch mask are investigated.

Wet chemical etching of ZnO films using NH x -based (NH4)2CO3 and NH4OH alkaline solution

In this paper, we deposited ZnO thin films by RF magnetron sputtering at room temperature from un-doped targets. Wet chemical etching of ZnO films in (NH4)2CO3 and NH4OH solutions were examined. For comparison, hydrochloric acid was also used as an etchant. The NH x -based alkaline solutions provide well-controlled etching rate, and smooth surface and sidewall profiles. Although NH x -based alkaline solution etch rates for ZnO were relatively low, they were enhanced with the use of a H3O stabilizer. In this case, the NH4OH solution went from reaction-dominant mode to diffusion-dominant mode, which is beneficial for smooth surface morphology.

Control of Sidewall Profile in Dry Plasma Etching of Polyimide

Spin-on polyimide is an organic thin film often used as a sacrificial layer for surface micromachining due to its high thermal stability, ease of removal, and compatibility with many materials and processes used in the realization of microelectromechanical systems (MEMS). The incorporation of sloped sidewalls in polyimide for fabricating pedestal structures is crucial in order to provide strong anchors in free-standing MEMS devices, especially in cases having a high aspect ratio and/or where structural materials have limited deposition conformality. This paper demonstrates a reliable reactive ion etching (RIE) methodology for tuning the polyimide sidewall angle, ranging from a vertical sidewall up to an angle of about 25° from the vertical. The key modifications to the process parameter space include changes to the process temperature and chamber pressure. This paper also presents a novel lift-off process, which is based on the use of an interfacial polymer layer to facilitate removal of an overlying silicon oxide hard mask. This procedure allows polyimide sacrificial layers employing a silicon oxide hard mask to be used on samples that have exposed silicon oxide layers elsewhere on the chip that are required to remain intact during hard mask removal. Therefore, this lift-off process is applicable in situations where the silicon oxide hard mask removal cannot be accomplished by wet etching in hydrofluoric acid solutions.

Optimized process for fabrication of free-standing silicon nanophotonic devices.

A detailed procedure is presented for fabrication of free-standing silicon photonic devices that accurately reproduces design dimensions while minimizing surface roughness. By reducing charging effects during inductively coupled-plasma reactive ion etching, undercutting in small, high-aspect ratio openings is reduced. Slot structures with a width as small as 40 nm and an aspect ratio of 5.5:1 can be produced with a nearly straight, vertical sidewall profile. Subsequent removal of an underlying sacrificial silicon dioxide layer by wet-etching to create free-standing devices is performed under conditions which suppress attack of the silicon. Slotted one-dimensional photonic crystal cavities are used as sensitive test structures to demonstrate that performance specifications can be reached without iteratively adapting design dimensions; optical resonance frequencies are within 1% of the simulated values and quality factors on the order of 105 are routinely attained.

Subwavelength grating microlens with taper-resistant characteristics.

The subwavelength grating microlens has attracted much attention due to its variety of potential applications. Instead of the vertical sidewall profile normally considered by most recent works, a tapered sidewall profile is often obtained during current fabrication processes, especially during the fabrication of high aspect ratio structures. In this work, we have discovered that a tapered sidewall profile may have a significant destructive effect on the concentration properties of subwavelength concentrating lenses/metasurfaces. This is caused by the phase shift from the tapered profile that affects each individual phase shifter. More interestingly, we have further discovered that there exist some period/fill-factor combinations for phase shifters that "resist" the phase shift from the tapered structure. This study will provide an important avenue for the design of subwavelength concentrating lenses/metasurfaces when dealing with the tapered sidewall profile.

Reactive Ion Etching Process of Micro Mechanical Pendulum

This paper describes the reactive ion etching (RIE) technique of micro mechanical pendulum chip. Micro mechanical pendulum chip processed by the RIE has excellent performances and surface of the chip is smoother than the chip by wet etching. Properties of chip are closely associated with the process parameters. Reactive ion etching technique improves the problems such as intricate lateral etching and surface deficiency of the wet etching. On the basis of method and many experiments of the ion etching, relation between etching rate, etching uniformity, sidewall profiles and process parameters was analyzed and a set process parameters with greater etching effect was obtained. The set process parameters includes etching depth 55μm, etching uniformity (U) 0.63% and selectivity (P) 90:1, etching rate (V) 5.75μm/min, verticality of sidewall 90°±1°.

Integration of Chemically Amplified Photoresist and High-Speed Copper Plating Products for Advanced Packaging Applications

Advanced packaging technologies require materials which will allow for better resolution of patterns associated with the ever more challenging device architecture, along with materials that will allow for higher throughput. Device throughput can be increased with imaging materials that have higher sensitivity and metallization chemistries with faster electrodeposition rates. Chemically amplified photoresists offer the advantages of excellent sensitivity and resolution with good process margins, coupled with excellent stripping performance and plating bath compatibility for the film thicknesses that are required in packaging applications. Electrolytic copper plating products with fast deposition rates are a key factor in decreasing wafer plating time and increasing throughput. However, it is the integration of the photoimaging material and the subsequent plating chemistry that is essential in producing metallized structures for copper pillar and solder applications. Because the profile of the resist image is directly transferred during the electroplating process, it is critical to have a well formed image that is resistant to the plating chemistry. Plating bath contamination and resist strippability are other key factors in producing void-free, defect-free structures. Dow's newly introduced chemically amplified material is capable of film thicknesses from 30um to 80um by a single coating process with good uniformity. Imaging and process latitude are demonstrated at 40um and 65um thicknesses with emphasis on sidewall profiles and sensitivity. Further, the photoresist compatibility with INTERVIA™ Cu 8540 Electroplating Copper Chemistry is shown, along with NIKAL™ BP Ni plating chemistry and SOLDERON™ BP TS 6000 SnAg plating chemistry compatibility. The improvements in product line from Dow's INTERVIA™ Cu 8540 to INTERVIA™ 9000 Electroplating Copper Chemistry is also demonstrated in the paper, with thickness uniformity, high plating speed, and tunable morphology highlighted for various applications. The power of integration has enabled the development of this suite of products designed for compatibility and superior performance for advanced packaging technologies. ™ Trademark of The Dow Chemical Company

Silicon nanostructures with very large negatively tapered profile by inductively coupled plasma-RIE

Dry etching of silicon has been extensively studied, mostly with a goal of obtaining perfectly vertical sidewalls with high aspect ratio. Yet, sloped sidewall with a negative taper angle (i.e., diameter/width decreases linearly with depth) may find various applications. However, the systematic study on the etching process development to obtain such a profile is rather scarce. In this work, the authors present a controlled and reproducible fabrication process to achieve silicon nanostructures with negatively tapered sidewall profile using inductively coupled plasma-reactive ion etching with C4F8 and SF6 gas. The plasma etching parameters have been thoroughly optimized in order to avoid the undercut or curved reentrant profile due to isotropic etching, so as to achieve a negatively tapered profile. The influence of the plasma etching parameters, especially the radio freguency power and C4F8/SF6 gas flow ratio, on the etching rate and the sidewall taper angle has been analyzed. With an optimal etching recipe, the silicon nanostructures with an unprecedented large 10° negative taper angle were achieved. These results were demonstrated on different structure sizes of 500 nm, 700 nm, and 1.2 μm diameters.

High-aspect-ratio photoresist processing for fabrication of high resolution and thick micro-windings

DC winding losses remain a major roadblock in realizing high efficiency micro-magnetic components (inductors/transformers). This paper reports an optimized photoresist process using negative tone and acrylic based THB-151N (from JSR Micro), to achieve one of the highest aspect ratio (17:1) and resolution (~5 µm) resist patterns for fabrication of thick (~80 µm) micro-winding using UV lithography. The process was optimized to achieve photoresist widths from 5 µm to 20 µm with resist thickness of ~85 µm in a single spin step. Unlike SU-8, this resist can be readily removed and shows a near-vertical (~91°) electroplated Cu side-wall profile. Moreover, the high resolution compared to available resist processes enables a further reduction in the footprint area and can potentially increase the number of winding thereby increasing the inductance density for micro-magnetic components. Resistance measurements of electroplated copper winding of air-core micro-inductors within the standard 0402 size (0.45 mm2 footprint area) suggested a 42% decrease in resistance (273 mΩ–159 mΩ) with the increase in electroplated Cu thickness (from 50 µm to 80 µm). Reduction of the spacings (from 10 µm to 5 µm) enabled further miniaturisation of the device footprint area (from 0.60 mm2 to 0.45 mm2) without significant increase in resistance.

Dummy Poly Gate Removal Scheme at Finfet

The technology of High-k/Metal Gate has led to the continuity of device scaling and enabled the prolongation of Moore’s Law towards the 40 nm and beyond nodes. The High-k first/Gate last approach (Dummy poly gate removal (DPGR)) has been widely adopted since it can better control the transistor threshold voltage (Vt), hence yielding the better electrical performance. However, this approach requires more complex process engineering at 3D structure. Both perfect physical structure and good electronic performance are challenging for dummy poly gate removal process [1]. As is well known, both dry etching and wet etching can effectively remove polysilicon. However, both schemes are incapable in some aspects. For example, traditional dry etching scheme might degrade electrical performance by damaging ILD and gate oxide layer, ending up with worse NBTI and PBTI performance. On the other hand, wet clean process is hard to control profile and cannot effectively remove the top layer of polysilicon which is doped by implant process. To balance these factors, partial dry etching/partial wet clean process was used for dummy poly removal process. However, this scheme could NOT fully avoid the disadvantage of both wet etching and dry etching, such as PID to degrade the device performance, ILD/SiN spacer loss, and the discontinuous sidewall profile. Besides, its too short queue - time and lower throughput are also the concerns [2]. We introduced one fully dry etching scheme to remove dummy gate polysilicon at FinFET. The method is based on the commercial CDE (chemical downstream) etcher. This is a kind of remote plasma etcher, which can effectively filter high energy ions and electrons, reduce the electron temperature to zero. The most magical and the remarkable difference with other remote plasma etcher come from the fact that, the fresh radical can be renewed after filtering out and before etching process. By controlling the types of radical, ratio, flow rate, energy distribution, even angle distribution, and the selectivity could be significantly improved. At 3D structure dummy poly gate removal process, this approach can realize zero material loss for both gate oxide and spacer SiN. The ILD loss could be neglected, mainly coming from the break-through step. As compared with the above CDE etcher, another CDE plasma etcher was used for the purpose of dummy poly gate removal, but both the selectivity and the overall physical results could not process specifications. This manuscript focuses on the full dry etching to remove dummy poly gate by commercial CDE etcher, the corresponding advantages and characteristics will be introduced and analyzed. Results show such scheme is significantly superior to the traditional dry etching, wet etching or the hybrid scheme from the point of view of free plasma damage, rigorously controlled material loss, queue time control and throughput. [1] P. Lim et al, USP, 7871915 B2 “Method for forming metal gates in a gate last process”, 2011 [2] Guang Yaw HWang, Solid State Phenomena, Vol.187, 57-60 “A Hybrid Dry-Wet Approach for Removal of a Dummy Polysilicon Gate in a Replacement Metal Gate Scheme” ， 2012

Fabrication of metallic nanodisc hexagonal arrays using nanosphere lithography and two-step lift-off

Nanosphere lithography (NSL) has been widely used as an inexpensive method to create periodic arrays of metallic nanoparticles or nanodiscs on substrates. However, most nanodisc arrays derived from a NSL template are restricted to hexagonally-ordered triangular arrays because the metal layer is deposited onto the interstices between the nanospheres. Metallic nanodisc arrays with the same arrangement as the original nanosphere array have been rarely reported. Here, we demonstrate a facile, low-cost method to fabricate large-area hexagonal arrays of metallic nanodiscs using an NSL template combined with a two-step lift-off process. We employ a bi-layer of two dissimilar metals to create a re-entrant sidewall profile to undercut the sacrificial layer and facilitate the final lift-off of the metallic nanodiscs. The quality of the nanodisc pattern and the array periodicity is determined using statistical image analysis and compared to the original nanosphere array in terms of size distribution, surface smoothness, and array pitch. This nanodisc array is used as an etch mask to create a vertically-aligned Si nanowire array. This combined approach is a scalable and inexpensive fabrication method for creating relatively large-area, ordered arrays of various nanostructures.

Development of a facile block copolymer method for creating hard mask patterns integrated into semiconductor manufacturing

Our goal is to develop a facile process to create patterns of inorganic oxides and metals on a substrate that can act as hard masks. These materials should have high etch contrast (compared to silicon) and so allow high-aspect-ratio, high-fidelity pattern transfer whilst being readily integrable in modern semiconductor fabrication (FAB friendly). Here, we show that ultra-small-dimension hard masks can be used to develop large areas of densely packed vertically and horizontally orientated Si nanowire arrays. The inorganic and metal hard masks (Ni, NiO, and ZnO) of different morphologies and dimensions were formed using microphase-separated polystyrene-b-poly(ethylene oxide) (PS-b-PEO) block copolymer (BCP) thin films by varying the BCP molecular weight, annealing temperature, and annealing solvent(s). The self-assembled polymer patterns were solvent-processed, and metal ions were included into chosen domains via a selective inclusion method. Inorganic oxide nanopatterns were subsequently developed using standard techniques. High-resolution transmission electron microscopy studies show that high-aspect-ratio pattern transfer could be affected by standard plasma etch techniques. The masking ability of the different materials was compared in order to create the highest quality uniform and smooth sidewall profiles of the Si nanowire arrays. Notably good performance of the metal mask was seen, and this could impact the use of these materials at small dimensions where conventional methods are severely limited.

Experimental study on longitudinal and transverse temperature distribution of sidewall confined ceiling jet plume

This paper investigates the longitudinal and transverse temperature profiles of a strong plume impinging flow, induced by a turbulent porous gas burner impinging on the sidewall confined ceiling of a long-narrow tunnel-like structure. A series of model scale experiments were conducted for fires against a tunnel sidewall with increasing vertical burner heights (0, 0.17 and 0.35m), 8 different HRRs (heat release rate) from 15.94 to 106.28kW were used. Measurements of the vertical temperature profiles against the sidewall and radial horizontal temperature profiles under the ceiling are presented. Results show that for the strong impingement plume, the temperatures at the impingement point can be well correlated by the three-regime of buoyant plume, intermittent flame and continuous flame. The horizontal temperature profiles under the ceiling show obviously asymmetric. It is confirmed that the characteristic length scale of plume radius at ceiling level is sufficiently applicable for predicting the ceiling excess temperatures of strong plume impingement flow, and the correlations of the ceiling excess temperature in both transverse and longitudinal directions are proposed and validated by comparing them with previous research.

Effects of shielding coatings on the anode shaping process during counter-rotating electrochemical machining

Electrochemical machining (ECM) has been widely used in the aerospace, automotive, defense and medical industries for its many advantages over traditional machining methods. However, the machining accuracy in ECM is to a great extent limited by the stray corrosion of the unwanted material removal. Many attempts have been made to improve the ECM accuracy, such as the use of a pulse power, passivating electrolytes and auxiliary electrodes. However, they are sometimes insufficient for the reduction of the stray removal and have their limitations in many cases. To solve the stray corrosion problem in CRECM, insulating and conductive coatings are respectively used. The different implement processes of the two kinds of coatings are introduced. The effects of the two kinds of shielding coatings on the anode shaping process are investigated. Numerical simulations and experiments are conducted for the comparison of the two coatings. The simulation and experimental results show that both the two kinds of coatings are valid for the reduction of stray corrosion on the top surface of the convex structure. However, for insulating coating, the convex sidewall becomes concave when the height of the convex structure is over 1.26 mm. In addition, it is easy to peel off by the high-speed electrolyte. In contrast, the conductive coating has a strong adhesion, and can be well reserved during the whole machining process. The convex structure fabricated by using a conductive iron coating layer presents a favorable sidewall profile. It is concluded that the conductive coating is more effective for the improvement of the machining quality in CRECM. The proposed shielding coatings can also be employed to reduce the stray corrosion in other schemes of ECM.

N-type ohmic contacts to undoped GaAs/AlGaAs quantum wells using only front-sided processing: application to ambipolar FETs

We report the development of a simple and reliable, front-sided-only fabrication technique for n-type ohmic contacts to two-dimensional electron gases (2DEGs) in undoped GaAs/AlGaAs quantum wells. We have adapted the well-established recessed ohmic contacts/insulated metal gate technique for inducing a 2DEG in an undoped triangular well to also work reliably for undoped square quantum wells. Our adaptation involves a change in the procedure for etching the ohmic contact pits to optimise the etch side-wall profile and depth. As an application of our technique, we present a front-side-gated ambipolar field effect transistor (FET), where both 2D electron and hole gases can be induced in the same quantum well. We present results of low-temperature (0.3 K - 4 K) transport measurements of this device, including assessment of the n-type ohmic contact quality. On the basis of our findings, we discuss why the fabrication of these contacts is difficult and how our technique circumvents the challenges.

Improved optical and electrical performances of GaN-based light emitting diodes with nano truncated cone SiO2 passivation layer

GaN-based light emitting diodes (LEDs) with nano truncated cone SiO2 passivation layer via laser interference lithography and inductively coupled plasma dry etching technology were fabricated. The sidewall profile of the nano truncated cones was optimized by adjusting the etching process to obtain high fill factor. The light output power and electroluminescence intensity of the LEDs with textured SiO2 surface show better results than the conventional LEDs without SiO2 layer. At an injection current of 20 mA, the enhancement of the light output power is about 64 %. Moreover, the reverse leakage current, under a reverse bias of −5 V, is obviously reduced in contrast to the conventional LEDs. The method of texturing the passivation layers is proved to be an alternative method to improve both the optical and electrical performances of GaN-based LEDs.

Computational study of the CF4 /CHF3 / H2 /Cl2 /O2 /HBr gas phase plasma chemistry

A modelling study is performed of high-density low-pressure inductively coupled CF4/CHF3/H2/Cl2/O2/HBr plasmas under different gas mixing ratios. A reaction set describing the complete plasma chemistry is presented and discussed. The gas fraction of each component in this mixture is varied to investigate the sensitivity of the plasma properties, like electron density, plasma potential and species densities, towards the gas mixing ratios. This research is of great interest for microelectronics applications because these gases are often combined in two (or more)-component mixtures, and mixing gases or changing the fraction of a gas can sometimes yield unwanted reaction products or unexpected changes in the overall plasma properties due to the increased chemical complexity of the system. Increasing the CF4 fraction produces more F atoms for chemical etching as expected, but also more prominently lowers the density of Cl atoms, resulting in an actual drop in the etch rate under certain conditions. Furthermore, CF4 decreases the free electron density when mixed with Cl2. However, depending on the other gas components, CF4 gas can also sometimes enhance free electron density. This is the case when HBr is added to the mixture. The addition of H2 to the gas mixture will lower the sputtering process, not only due to the lower overall positive ion density at higher H2 fractions, but also because more H+, and are present and they have very low sputter yields. In contrast, a larger Cl2 fraction results in more chemical etching but also in less physical sputtering due to a smaller abundance of positive ions. Increasing the O2 fraction in the plasma will always lower the etch rate due to more oxidation of the wafer surface and due to a lower plasma density. However, it is also observed that the density of F atoms can actually increase with rising O2 gas fraction. This is relevant to note because the exact balance between fluorination and oxidation is important for fine-tuning the overall etch rate and for control of the sidewall profile. Finally, HBr is often used as a chemical etcher, but when mixed with F- or Cl-containing gases, HBr creates the same diluting effects as Ar or He, because a higher fraction results in less chemical etching but more (physical) sputtering.

Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND

In vertical gate (VG)-type 3-D NAND, reducing either channel polycrystalline silicon (PL) or intersilicon dioxide (OX), or both, allows packing more cells in a fixed volume. However, when programming cells in such an array, the neighbor top/bottom cells suffer significant threshold voltage ( $V_{t}$ ) shift due to two unique mechanisms. The first mechanism is the fringing field of the programmed charges (Z-interference), whereas the second one is the degraded inhibited potential affected by the programmed PL channel, which is grounded (Z-disturbance). Z-interference happens before Z-disturbance, so it is more critical to the memory window. Optimizing PL/OX thickness or engineering the PL sidewall profile can balance the constraint of Z-interference and the demand of higher memory density. They are important guidelines when designing VG-type 3-D NAND memory.

Tunable top-down fabrication and functional surface coating of single-crystal titanium dioxide nanostructures and nanoparticles.

Titanium dioxide (TiO2) is a key component of diverse optical and electronic applications that exploit its exceptional material properties. In particular, the use of TiO2 in its single-crystalline phase can offer substantial advantages over its amorphous and polycrystalline phases for existing and yet-to-be-developed applications. However, the implementation of single-crystal TiO2 has been hampered by challenges in its fabrication and subsequent surface functionalization. Here, we introduce a novel top-down approach that allows for batch fabrication of uniform high-aspect-ratio single-crystal TiO2 nanostructures with targeted sidewall profiles. We complement our fabrication approach with a functionalization strategy that achieves dense, uniform, and area-selective coating with a variety of biomolecules. This allows us to fabricate single-crystal rutile TiO2 nanocylinders tethered with individual DNA molecules for use as force- and torque-transducers in an optical torque wrench. These developments provide the means for increased exploitation of the superior material properties of single-crystal TiO2 at the nanoscale.