Dummy Poly Gate Removal Scheme at Finfet

Abstract

The technology of High-k/Metal Gate has led to the continuity of device scaling and enabled the prolongation of Moore’s Law towards the 40 nm and beyond nodes. The High-k first/Gate last approach (Dummy poly gate removal (DPGR)) has been widely adopted since it can better control the transistor threshold voltage (Vt), hence yielding the better electrical performance. However, this approach requires more complex process engineering at 3D structure. Both perfect physical structure and good electronic performance are challenging for dummy poly gate removal process [1]. As is well known, both dry etching and wet etching can effectively remove polysilicon. However, both schemes are incapable in some aspects. For example, traditional dry etching scheme might degrade electrical performance by damaging ILD and gate oxide layer, ending up with worse NBTI and PBTI performance. On the other hand, wet clean process is hard to control profile and cannot effectively remove the top layer of polysilicon which is doped by implant process. To balance these factors, partial dry etching/partial wet clean process was used for dummy poly removal process. However, this scheme could NOT fully avoid the disadvantage of both wet etching and dry etching, such as PID to degrade the device performance, ILD/SiN spacer loss, and the discontinuous sidewall profile. Besides, its too short queue - time and lower throughput are also the concerns [2]. We introduced one fully dry etching scheme to remove dummy gate polysilicon at FinFET. The method is based on the commercial CDE (chemical downstream) etcher. This is a kind of remote plasma etcher, which can effectively filter high energy ions and electrons, reduce the electron temperature to zero. The most magical and the remarkable difference with other remote plasma etcher come from the fact that, the fresh radical can be renewed after filtering out and before etching process. By controlling the types of radical, ratio, flow rate, energy distribution, even angle distribution, and the selectivity could be significantly improved. At 3D structure dummy poly gate removal process, this approach can realize zero material loss for both gate oxide and spacer SiN. The ILD loss could be neglected, mainly coming from the break-through step. As compared with the above CDE etcher, another CDE plasma etcher was used for the purpose of dummy poly gate removal, but both the selectivity and the overall physical results could not process specifications. This manuscript focuses on the full dry etching to remove dummy poly gate by commercial CDE etcher, the corresponding advantages and characteristics will be introduced and analyzed. Results show such scheme is significantly superior to the traditional dry etching, wet etching or the hybrid scheme from the point of view of free plasma damage, rigorously controlled material loss, queue time control and throughput. [1] P. Lim et al, USP, 7871915 B2 “Method for forming metal gates in a gate last process”, 2011 [2] Guang Yaw HWang, Solid State Phenomena, Vol.187, 57-60 “A Hybrid Dry-Wet Approach for Removal of a Dummy Polysilicon Gate in a Replacement Metal Gate Scheme” ， 2012