Sidewall Damage Research Articles

Low damage ultra-low-k patterning using a high boiling point organic (HBPO) combined with NF3

The plasma etching of a k = 2.3 periodic mesoporous ultra-low-k dielectric is studied, using a new gas mixture made of a high boiling point organic (HBPO) reagent and NF3. By decreasing the wafer temperature below 10 °C, the onset of micro-capillary condensation is observed, inducing pore wall passivation (∼10 °C < T < ∼ −20 °C, refractive index between 1.27 and 1.38) then complete pore filling (T < −20 °C, refractive index ∼1.38). The HBPO condensed phase is found to be stable for more than one minute for temperatures below −30 °C. The patterning capabilities of the discharge are studied on a 45 nm half pitch vehicle, leading to plasma etch conditions giving good morphological profiles and reduced sidewall damage. Due to HBPO condensation, the pristine carbon content of the film is maintained, preventing any drift in k-value. The absence of damage also prevents significant modifications of the mechanical properties of the ultra-porous low-k material. The present work shows that electrically and mechanically safe low-k etching can be achieved with an NF3/HBPO plasma, around −30 °C.

Experimental simulation investigation on rockburst induced by spalling failure in deep circular tunnels

Spalling and rockburst are two common failure modes in deep hard-rock tunnels and they exhibit a strong correlation. In this paper, the process of rockburst induced by spalling is investigated. The uniaxial compressive strength and rockburst tendency of red sandstone are measured. Four different initial stress conditions are set up, and cubic red sandstone samples with a prefabricated hole are tested by a true-triaxial test system. During the experimental process, the failure of the hole sidewall is monitored and recorded in real time by a micro-camera. The process of rockburst induced by spalling damage in deep hard-rock tunnels is reproduced, and the mechanism by which spalling damage on induces rockburst is revealed. In addition, the evolution process and failure characteristics of rockburst induced by spalling damage are analysed. The experimental results indicated that the red sandstone has a moderate rockburst tendency, and its rockburst process can be divided into four periods: the calm period, the small grain ejection & spalling damage period, the slab buckling & fragment ejection period and the violent ejection period. The mechanism of spalling damage on inducing rockburst is mainly embodied in two aspects: promoting large buckling deformations (providing energy for rockburst) and to weakening the strength of the rock mass (creating conditions for the suddenly release of energy). The effect of lateral stress on spalling damage and rockburst is more obvious than that of axial stress, and the severity of rockburst can be significantly reduced by increasing the lateral stress. The diameter of the hole has a strength size effect on the sidewall damage, producing a certain inhibitory effect on the spalling damage and rockburst. Smaller lateral stress corresponds with greater depths of the V-shaped notch and much smaller width-to-length ratios in the rock fragments.

High-aspect ratio micro- and nanostructures enabled by photo-electrochemical etching for sensing and energy harvesting applications

Photo-electrochemical (PEC) etching can produce high-aspect ratio features, such as pillars and holes, with high anisotropy and selectivity, while avoiding the surface and sidewall damage caused by traditional deep reactive ion etching (DRIE) or inductively coupled plasma (ICP) RIE. Plasma-based techniques lead to the formation of dangling bonds, surface traps, carrier leakage paths, and recombination centers. In pursuit of effective PEC etching, we demonstrate an optical system using long wavelength (λ = 975 nm) infra-red (IR) illumination from a high-power laser (1–10 W) to control the PEC etching process in n-type silicon. The silicon wafer surface was patterned with notches through a lithography process and KOH etching. Then, PEC etching was introduced by illuminating the backside of the silicon wafer to enhance depth, resulting in high-aspect ratio structures. The effect of the PEC etching process was optimized by varying light intensities and electrolyte concentrations. This work was focused on determining and optimizing this PEC etching technique on silicon, with the goal of expanding the method to a variety of materials including GaN and SiC that are used in designing optoelectronic and electronic devices, sensors and energy harvesting devices.

The role of plasma analytics in leading‐edge semiconductor technologies

Plasma patterning processes play a key role in modern Ultra Large Scale Integration (ULSI) device fabrication. With further scaling of device dimensions, plasma process characteristics become more and more the limiting factor in pattern minimization, not least due to parasitic effects caused by different plasma properties. Such effects are geometrical deviations in the etch profiles, the loss of critical dimensions, the undercut as well as the most critical sidewall damage while etching trenches and vias to fabricate the circuit contact and metallization system. Especially for modern dielectric materials on the base of carbon‐doped silica these drawbacks are much pronounced and worsen performance and power consumption of microelectronic devices. Finally, the charge damage of thin gate oxides during plasma processing results in reduced reliability and functionality of microelectronic devices. The complex interactions between conditions in the plasma bulk and the impacts on the wafer surface are not yet understood completely. With respect to the increasing complexity of modern semiconductor plasma etch equipment, the optimization of patterning processes using the empirical method becomes more and more impossible. This paper overviews typical challenges during plasma patterning processes in 28 nm and 22 nm technology nodes by means of today's Back‐End of Line integration schemes. Different plasma diagnostic methods provide an insight into the physical and chemical conditions of different etch chambers and their influence on process results and damaging behaviour.

Neutral beam and ICP etching of HKMG MOS capacitors: Observations and a plasma-induced damage model

In this study, TiN/HfO2/Si metal-oxide-semiconductor (MOS) capacitors were etched by a neutral beam etching technique under two contrasting conditions. The configurations of neutral beam etching technique were specially designed to demonstrate a “damage-free” condition or to approximate “reactive-ion-etching-like” conditions to verify the effect of plasma-induced damage on electrical characteristics of MOS capacitors. The results show that by neutral beam etching (NBE), the interface state density (Dit) and the oxide trapped charge (Qot) were lower than routine plasma etching. Furthermore, the decrease in capacitor size does not lead to an increase in leakage current density, indicating less plasma induced side-wall damage. We present a plasma-induced gate stack damage model which we demonstrate by using these two different etching configurations. These results show that NBE is effective in preventing plasma-induced damage at the high-k/Si interface and on the high-k oxide sidewall and thus improve the electrical performance of the gate structure.

Fabrication of Novel MEMS Microgrippers by Deep Reactive Ion Etching With Metal Hard Mask

The fabrication of a novel class of microgrippers is demonstrated by means of bulk microelectromechanical systems (MEMS) technology using silicon on insulator wafer substrates and deep reactive ion etching. Hard masking is implemented to maximize the selectivity of the bulk etching using sputtered aluminum and aluminum–titanium thin films. The micro-roughness problem related to the use of metal mask is addressed by testing different mask combinations and etching parameters. The O2 flow, SF6 pressure, wafer temperature, and bias power are examined, and the effect of each parameter on micro-masking is assessed. Sidewall damage associated with the use of a metal mask is eliminated by interposing a dielectric layer between silicon substrate and metal mask. Dedicated comb-drive anchors are implemented to etch safely both silicon sides down to the buried oxide, and to preserve the wafer integrity until the final wet release of the completed structures. A first set of complete devices is realized and tested under electrical actuation. [2017-0039]

Impact of Wire Geometry on Interconnect &lt;italic&gt;RC&lt;/italic&gt; and Circuit Delay

We investigate the impact of wire geometry on the resistance, capacitance, and RC delay of Cu/low-k damascene interconnects for fixed line-to-line pitch. The resistance is computed by applying a semiempirical resistivity model, calibrated to Cu damascene wires, integrated with a Ru-based liner, currently investigated for the 7 nm logic technology node. The capacitance is simulated by means of a 2D field solver (Raphael) by Synopsys. The impact of line dimensions is analyzed for the case of 32 nm pitch interconnects, which are representative of the 7 nm logic technology node. We show that for aspect ratios greater than 1, the resistance is more sensitive to variations of the line width rather than of the line height, because of the higher surface scattering induced by the sidewall interfaces, which are closer to each other compared with the top and bottom interfaces. For capacitance, low-k sidewall damage exacerbates capacitance sensitivity to line dimensions and, for typical interconnect schemes, the impact of line width variations dominates over variations of the line height. We demonstrate that for a given pitch and dielectric stack height, the RC delay can be significantly reduced by targeting wider and deeper damascene trenches, that is, by trading capacitance for resistance, and that an optimal wire geometry for RC delay minimization exists. In addition, we show that a given RC delay can be achieved with several geometries and, therefore, R and C pairs, which represents a useful degree of freedom for designers to optimize system-level performance. As an application, we analyze a possible 7 nm technology scenario and show that wide and deep damascene trenches can mitigate the impact of the increased wire resistance on circuit delay.

Using Two-Step Mesa to Prevent the Effects of Sidewall Defects on the GaN p-i-n Diodes

In this paper, the two-step mesas of quasi-vertical GaN p-i-n diodes grown on pattern sapphire substrates (PSSs) with a 3- $\mu \text{m}~{i}$ -layer were defined by two-step dry etching to different depths to prevent the effects of sidewall damages. As compared with the one-step mesa device, the two-step mesa devices show lower reverse leakage currents, lower capacitances, lower specific ON-resistances, and higher reverse breakdown voltages. Furthermore, one of the two-step mesa devices with plasma treatment exhibits about two orders of magnitude of reduction in the leakage current at −100 V, a breakdown voltage of 495 V, and a specific ON-resistance ( $\text{R}_{\rm{\scriptscriptstyle ON}}\vphantom {\sum ^{R^{R}}}\text{A}$ ) of 0.27 $\text{m}\Omega $ -cm $^{ { {2}}}$ . Baliga’s figures of merit ( $\text{V}_{\rm { {B}}}^{ { {2}}}/\text{R}_{\rm{\scriptscriptstyle ON}}\vphantom {\sum _{R_{R_{R}}}}\text{A}$ ) of 0.908 GW/cm $^{ { {2}}}$ , which is the highest value reported for the fabricated GaN p-i-n diodes grown on sapphire, is achieved for the GaN p-i-n diode grown on PSS with a two-step mesa and plasma treatment.

(Invited) Towards a Vertical and Damage Free Post-Etch InGaAs Fin Profile: Dry Etch Processing, Sidewall Damage Assessment and Mitigation Options

Based on current projections, III-Vs are expected to replace Si as the n-channel solution in FinFETs at the 7nm technology node. The realisation of III-V FinFETs entails top-down fabrication via dry etch techniques. Vertical fins in conjunction with high quality sidewall MOS interfaces are required for high-performance logic devices. This, however, is difficult to achieve with dry etching. Highly anisotropic etching required of vertical fins is concomitant with increased damage to the sidewalls, resulting in the quality of the sidewall MOS interface being compromised. In this work, we address this challenge in two stages by first undertaking a systematic investigation of dry etch processing for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. In the second stage, dry etch process optimisation and post-etch sidewall passivation schemes are explored to mitigate the damage arising from anisotropic etching required for the realisation of vertical fins.

Examining Foil Sidewall Damage During TEM Sample Preparation Using Gallium FIB and Needle Geometries

Examining Foil Sidewall Damage During TEM Sample Preparation Using Gallium FIB and Needle Geometries

Catalytic Activity Evaluation of Palladium Decorated Damaged Carbon Nanotube for Direct Ethanol Fuel Cells in Anode

The sp2 p-conjugative structure, that allows the carbon nanotube (CNT) interact with various compounds and metal nanoparticles (NPs) through p–p interaction. The damage of p-conjugative sidewall of CNT can hamper the overall anodic activity. The CNT, as base material, has been prepared through a conventional acid treatment method up to 15h; the higher degree of sidewall damage has been observed in last 5 hours during treatment period. The short and long term acid treated CNTs have been subsequently fabricated with palladium NPs (denoted as CNT/Pd and CNT–Pd, respectively) and employed as ethanol oxidation reaction (EOR) catalysts for direct ethanol fuel cells (DEFCs). The structural features of catalyst are characterized by several instrumental techniques. The Barrett–Joyner–Halenda pore volume of CNTs have been increased upon increasing acid treatment time from 0.326 cm³ g−1 (1h CNT), 0.381 cm³ g−1 (5h CNT), 0.488 cm³ g−1 (10h CNT) to 0.598 cm³ g−1 (15h CNT). The kinetic parameters including poisoning tolerance have also been hampered by the surface damage. The CNT/Pd and CNT–Pd are express higher electrocatalytic activity and poisoning tolerance than that of Pd/C while Pd mass loading remains in the same amount.

(Invited) Towards a Vertical and Damage Free Post-Etch InGaAs Fin Profile: Dry Etch Processing, Sidewall Damage Assessment and Mitigation Options

In an era of power-constrained transistor scaling, III-V semiconductors, with high electron velocities, appear promising as the n-channel solution in post-Si CMOS technologies [1]. To make this a reality, substantial undertaking has gone into finding solutions for the technological challenges facing III-V MOSFETs [1,2]. InGaAs, in particular, has been the centre of extensive research effort. This has led to the development of surface passivation measures capable of significantly minimizing the defects at the gate dielectric/III-V interface [3,4], ultra-low resistance source/drain contact technology [5], III-V heterointegration capability on Si substrates [6] and demonstration of record performing planar MOSFETs suited for high-performance and low-power logic [7-9]. Currently, InGaAs is being primed for entry into CMOS at the 7nm technology node and beyond. However, given the transition to FinFETs in CMOS technology [10], there is a need to develop dry etch processes capable of nanometer-scale fin definition in III-Vs. Key requirements of the dry etch process are vertical sidewalls and minimum etch damage. The former provides for efficient device electrostatics while the latter is required for a high quality sidewall MOS interface [11]. However, satisfying both criteria is challenging. Highly anisotropic dry etching required for sidewall verticality is more damaging due to the physical nature of the process. Unlike Si, the induced damage cannot be cured by post etch annealing in III-Vs [1]. In this talk we will first report on the dry etch processing systematically investigated for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. Fins were etched in InGaAs, masked with HSQ of nanometric linewidths, for a variety of dry etch gas chemistries using either a RIE or an ICP process. A fin profile within 3¢ª of vertical was achieved with an ICP etch process based around Cl2/CH4/H2 gas chemistry (Fig. 1a). Highly vertical 10nm fins with 16:1 aspect ratio, perhaps the highest aspect ratio, smallest critical dimension fins to date in InGaAs, have also been demonstrated using this chemistry (Fig. 1b). Impact of the various ICP processes were assessed on Al2O3/InGaAs(100) MOS capacitors subject to blanket etch processing prior to (NH4)2S wet treatment and ALD gate dielectric. Despite the promising fin profile, the Cl2/CH4/H2 based ICP process yielded a severely degraded CV characteristic, featuring a peak Dit that is ~5x higher than the control (unetched) sample (Fig. 2). TEM and AFM were used to further elucidate the impact of the various ICP etch processes on the physical properties of the Al2O3/InGaAs interface. The second part of the talk will focus on the mitigation of etch-induced sidewall damage via dry etch process optimization and sidewall passivation techniques. It will be demonstrated that the modification of Cl2/CH4/H2 gas chemistry to include O2 results in the substantial reduction of etch-induced damage, due to the lowering of the ICP power. A near-vertical sidewall profile similar to that obtained for the etch chemistry without O2 is further retained. Some examples of nanowires realized using this gas chemistry will also be shown. The sidewall damage arising from Cl2/CH4/H2/O2 etch chemistry will be assessed on both (100) and (110) oriented InGaAs. To alleviate the damage two post-etch sidewall passivation schemes were explored. The first was based on a photon-assisted hydrogenation process developed by Amethyst Research Inc., applied post-etch or post ALD high-k, and was investigated on Al2O3/InGaAs(100) MOS capacitors subject to Cl2/CH4/H2 blanket etch. The CV results indicated a larger reduction of etch damage for hydrogenation done post ALD high-k (Fig. 3). In the second approach, a wet “digital” etch surface clean was applied following a Cl2/CH4/H2/O2 blanket etch, resulting in a complete recovery of etch damage as determined from CV characteristics of Al2O3/InGaAs(100) MOS capacitor. The process was also investigated for (110) oriented InGaAs. Details of the passivation schemes and the associated results will be discussed further.

(Invited) An Industry Perspective on Atomic Layer Etching

As we celebrate the 50th anniversary of Moore’s Law, the scaling of transistors on a microprocessor at a two year cadence continues. While scaling of critical dimensions (CD) and pitch is widely recognized, the thickness of films that need to be patterned has also scaled down. Additionally, the etch stop films have also become thinner. With pitch scaling, the role of sidewall damage during plasma etch process has become more significant. As the films become thinner and damage free process become more relevant, atomic layer etch as a manufacturing option has become more attractive. This talk will evaluate different atomic layer etch options, discuss the respective pros and cons. Potential enabling examples of atomic layer etch will be presented focusing primarily on atomic layer control, damage reduction and extreme selecitivities.

Electrochemical activity evaluation of chemically damaged carbon nanotube with palladium nanoparticles for ethanol oxidation

The carbon nanotube (CNT) has unique electrical and structural properties due to it's sp2 π-conjugative structure that leads to the higher electrocatalysis. The π-conjugative structure, that allows the CNT interact with various compounds and metal nanoparticles (NPs) through π–π electronic interaction. However, the damage of π-conjugative sidewall of CNT that can be hinder the electrocatalytic activity has found. For this study, the CNT, as base material, has been prepared through a conventional acid treatment method up to 15 h; the higher degree of sidewall damage has been observed in last 5 h during treatment period. The short and long term acid treated (denoted as CNT and CNT–COOH, respectively) CNTs have been subsequently fabricated with palladium NPs (denoted as CNT/Pd and CNT–Pd, respectively) and employed as ethanol oxidation reaction (EOR) catalysts. The CNT–Pd displays a poor electrocatalytic performance towards EOR than that of CNT/Pd due to the damage of π-conjugative sidewall. The kinetic parameters including poisoning tolerance have also been hampered by the surface damage. The CNT/Pd (∼3.3 folds) and CNT–Pd (∼1.5 folds) are express higher electrocatalytic activity and poisoning tolerance than that of Pd/C while Pd mass loading remains in the same amount.

Effect of process parameters on sidewall damage in deep silicon etch

Sidewall damage caused in deep reactive ion silicon etch was investigated by varying etch cycle time, bias power, etch pressure and SF6 flow rate using the Bosch process in a uniquely designed, inductively coupled plasma reactor. The effects of these process parameters on the etch profile and sidewall angle were also studied for high density metal–insulator–metal capacitor structure. By choosing the proper etch cycle time of 2 s, it was observed that the sidewall damage was very sensitive to these etch process parameters. As bias power increased, the sidewall damage increased gradually. Especially, at the bias power of 500 W, a dual bowing shape with severe sidewall damage was seen, which might be due to a combination of two mechanisms: the formation of a redeposition region and a secondary ion etch effect. With increasing pressure, the sidewall damage was not always located in a specific depth range but distributed along almost the whole trench sidewall. An etch pressure below 80 mTorr was favorably recommended for reducing the extent of the sidewall damage. In addition, we found that an appropriate SF6 flow rate was also very beneficial to the realization of a smooth trench sidewall when it was controlled within an appropriate range. Based on these investigations, an acceptable etch condition could be selected to achieve a nearly vertical etch profile as well as a smooth sidewall surface.

Optimization of Etching Profile in Deep-Reactive-Ion Etching for MEMS Processes of Sensors

This paper reports the results of a study on the optimization of the etching profile, which is an important factor in deep-reactive-ion etching (DRIE), i.e., dry etching. Dry etching is the key processing step necessary for the development of the Internet of Things (IoT) and various microelectromechanical sensors (MEMS). Large-area etching (open area > 20%) under a high-frequency (HF) condition with nonoptimized processing parameters results in damage to the etched sidewall. Therefore, in this study, optimization was performed under a low-frequency (LF) condition. The HF method, which is typically used for through-silicon via (TSV) technology, applies a high etch rate and cannot be easily adapted to processes sensitive to sidewall damage. The optimal etching profile was determined by controlling various parameters for the DRIE of a large Si wafer area (open area > 20%). The optimal processing condition was derived after establishing the correlations of etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and SF6 gas flow rate. The processing-parameter-dependent results of the experiments performed for optimization of the etching profile in terms of etch rate, uniformity, and sidewall damage in the case of large Si area etching can be summarized as follows. When LF is applied, the platen power, coil power, and SF6 should be low, whereas the run pressure has little effect on the etching performance. Under the optimal LF condition of 380 Hz, the platen power, coil power, and SF6 were set at 115W, 3500W, and 700 sccm, respectively. In addition, the aforementioned standard recipe was applied as follows: run pressure of 4 Pa, C4F8 content of 400 sccm, and a gas exchange interval of SF6/C4F8 = 2 s/3 s.

Quantum cascade laser based monitoring of CF2 radical concentration as a diagnostic tool of dielectric etching plasma processes

Dielectric etching plasma processes for modern interlevel dielectrics become more and more complex by the introduction of new ultra low-k dielectrics. One challenge is the minimization of sidewall damage, while etching ultra low-k porous SiCOH by fluorocarbon plasmas. The optimization of this process requires a deeper understanding of the concentration of the CF2 radical, which acts as precursor in the polymerization of the etch sample surfaces. In an industrial dielectric etching plasma reactor, the CF2 radical was measured in situ using a continuous wave quantum cascade laser (cw-QCL) around 1106.2 cm−1. We measured Doppler-resolved ro-vibrational absorption lines and determined absolute densities using transitions in the ν3 fundamental band of CF2 with the aid of an improved simulation of the line strengths. We found that the CF2 radical concentration during the etching plasma process directly correlates to the layer structure of the etched wafer. Hence, this correlation can serve as a diagnostic tool of dielectric etching plasma processes. Applying QCL based absorption spectroscopy opens up the way for advanced process monitoring and etching controlling in semiconductor manufacturing.

Effect of feature size on dielectric nonlinearity of patterned PbZr0.52Ti0.48O3 films

Lead zirconate titanate, PZT (52/48), thin films with a PbTiO3 seed layer were patterned into features of different widths, including various sizes of squares and 100 μm, 50 μm, and 10 μm serpentine designs, using argon ion beam milling. Patterns with different surface area/perimeter ratios were used to study the relative importance of damage produced by the patterning. It was found that as the pattern dimensions decreased, the remanent polarization increased, presumably due to the fact that the dipoles near the feature perimeter are not as severely clamped to the substrate. This investigation is in agreement with a model in which clamping produces deep wells, which do not allow some fraction of the spontaneous polarization to switch at high field. The domain wall mobility at modest electric fields was investigated using the Rayleigh law. Both the reversible, εinit, and irreversible, α, Rayleigh coefficients increased with decreasing serpentine line width for de-aged samples. For measurements made immediately after annealing, εinit of 500 μm square patterns was 1510 ± 13; with decreasing serpentine line width, εinit rose from 1520 ± 10 for the 100 μm serpentine to 1568 ± 23 for the 10 μm serpentine. The irreversible parameter, α, for the square patterns was 39.4 ± 3.2 cm/kV and it increased to 44.1 ± 3.2 cm/kV as the lateral dimension is reduced. However, it was found that as the width of the serpentine features decreased, the aging rate rose. These observations are consistent with a model in which sidewall damage produces shallow wells that lower the Rayleigh constants of aged samples at small fields. These shallow wells can be overcome by the large fields used to measure the remanent polarization and the large unipolar electric fields typically used to drive thin film piezoelectric actuators.

Metallic 10 nm Diameter Magnetic Sensors and Large-Scale Ordered Arrays

Metallic nanowires with low resistivity were grown inside insulating aluminum oxide matrices that contained very uniform columnar nanopores (10.6+/1.7 nm diameters). These nanopores can be made with large-scale order (cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), which is desirable in applications such as hard drive read sensors and random access memories. The nanowires are grown by electrochemical deposition directly inside the alumina to avoid sidewall damage compared to nanostructures that are defined from films by lithographical patterning and etching. Specifically, trilayers of [Co(15 nm)/Cu(5 nm)/Co(10 nm)] were synthesized and measured to have 30 Ω resistance and 19% magnetoresistance. These parameters are desirable for read head sensors, especially because the nanowires described here have 1:1 aspect ratios, and 10× smaller areas and 100× lower resistances than conventional read sensors based on lithographically produced magnetic tunnel junctions. A new nanostamping technique is introduced, in which linear stamps with ordered cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> areas are imprinted onto aluminum precursors to produce ordered nanoporous aluminum oxide upon anodization. These stamps are substantially less-time consuming and cheaper to make than dot type stamps, and the order enables closely spaced arrays of CPP-GMR sensors for one-pass 2-D recording and cross recording. Importantly, the GMR sensors are grown directly into aluminum oxide with 20 nm separation. Therefore, a relatively large pattern (30 × 100 nm) can be used to produce three 10 nm-diameter GMR sensors without roughening or redeposition on sidewalls. The sensors are also already embedded in alumina for subsequent device processing.

Mechanism study of sidewall damage in deep silicon etch

The formation and etch mechanism of sidewall damage in deep silicon etch using standard Bosch process have been investigated in this work for the first time. The sidewall damage occurs at a certain depth where the sidewall is not sufficiently protected from lateral etch during long-time ion bombardment, and further, we demonstrate that the formation of sidewall damage is not only related to passivation film on the trench sidewall, but also closely relies on ion-enhanced etch mechanism. In addition, it is found that the starting depth of sidewall damage is almost inversely proportional to etch pressure and ion incidence angle, which can be attributed to a broader ion angular distribution (IAD) at higher chamber pressure. Then, a quantitative etch model based on IAD function has been also proposed to investigate the dependence of the starting depth of sidewall damage on ion incidence angle. Finally, by optimizing process parameters, high-quality etch profile without any observable sidewall damage has been successfully achieved at etch pressure of 60 mTorr.