Impact of Wire Geometry on Interconnect <italic>RC</italic> and Circuit Delay

Abstract

We investigate the impact of wire geometry on the resistance, capacitance, and RC delay of Cu/low-k damascene interconnects for fixed line-to-line pitch. The resistance is computed by applying a semiempirical resistivity model, calibrated to Cu damascene wires, integrated with a Ru-based liner, currently investigated for the 7 nm logic technology node. The capacitance is simulated by means of a 2D field solver (Raphael) by Synopsys. The impact of line dimensions is analyzed for the case of 32 nm pitch interconnects, which are representative of the 7 nm logic technology node. We show that for aspect ratios greater than 1, the resistance is more sensitive to variations of the line width rather than of the line height, because of the higher surface scattering induced by the sidewall interfaces, which are closer to each other compared with the top and bottom interfaces. For capacitance, low-k sidewall damage exacerbates capacitance sensitivity to line dimensions and, for typical interconnect schemes, the impact of line width variations dominates over variations of the line height. We demonstrate that for a given pitch and dielectric stack height, the RC delay can be significantly reduced by targeting wider and deeper damascene trenches, that is, by trading capacitance for resistance, and that an optimal wire geometry for RC delay minimization exists. In addition, we show that a given RC delay can be achieved with several geometries and, therefore, R and C pairs, which represents a useful degree of freedom for designers to optimize system-level performance. As an application, we analyze a possible 7 nm technology scenario and show that wide and deep damascene trenches can mitigate the impact of the increased wire resistance on circuit delay.