Side-contacted Field Effect Diode Research Articles

Capacitance–resistance modeling of an inverter based on a nanoscale side-contacted field-effect diode with an overshoot suppression approach

Capacitance–resistance modeling of an inverter based on a nanoscale side-contacted field-effect diode with an overshoot suppression approach

Noise-Immune 6T SRAM Bit-Cells Based on Side-Contacted FED

Modern system-on-chip (SoC) designers are trying to include more considerations in designing building blocks to present reliable integrated digital circuits as well as high-density ones. In this article, an innovative static random access memory (SRAM) bit-cell architecture is successfully designed based on the previously proposed side-contacted field effect diode (S-FED) using 180-nm technology. The device structure is optimized to satisfy high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio more than seven orders of magnitude. Behavioral modeling of S-FED in comparison with CMOS counterpart provides the capability of employing S-FED in the pull-down, pull-up, and pass-gate networks with identical geometry. The simplest triple S-FED-based bit-cell is designed to evaluate write and read logic 0/1 operations utilizing steady-state responses. Transient and ac analysis are also extracted from the six S-FED-based bit-cell to characterize SRAM fingerprints. Results demonstrate that the proposed bit-cell is noise-immune with maximum static noise margin (SNM) equal to 33.6% V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , high-speed with switching frequency of about 1.8 GHz (write) and 50 MHz (read), and low-power with static and dynamic power consumption lower than 10 nW and 5 nW/GHz, respectively. Moreover, SNM and Monte Carlo (MC) analyses reveal outstanding stability of the designed SRAM bit-cell based on S-FEDs when extreme variability scenarios induce device degradation.

Numerical solution of the Schrödinger equation in nanoscale side-contacted FED applying the finite-difference method

Numerical approaches play an outstanding role in solution of quantum mechanical problems with due attention to the complexity of analytic solutions for open systems. This paper studies quantum characteristics of the previously proposed side-contacted field-effect diode (S-FED) as an emerging device in the modern system-on-chips (SoCs) using the finite-difference method (FDM). The characteristics obtained by solving the Schrödinger equation and regarding the distinguished potentials in ON and OFF states include energy levels and time-independent/dependent wave functions. The cosine dependency of eigenvalues on longitudinal position conveys level broadening in high states stringing a sequence of probability oscillations in the ON state. Remarkable potential barriers in the OFF state result in an inability of electron movement from source to drain in low energies; nevertheless, by overcoming the total energy to potential barrier, the transport is feasible in higher states, so that minority carriers contribute to transport mechanism in the highest energies.

Performance comparison of 6T SRAM bit-cells based on side-contacted FED and CMOS

Designing a Static Random-Access Memory (SRAM) cell configuration that copes with conventional complementary metal-oxide-semiconductor (CMOS) constraints on the cell area is desired to satisfy high packing density in integrated digital circuits. This paper analyzes and compares performance parameters of 6T SRAM bit-cells based on the side-contacted field-effect diode (S-FED) and conventional CMOS at 180 nm technology node. Steady-state responses demonstrate that in the worst-case, by applying weak logic 0/1 to the bit-lines, strong logic data is stored in the S-FED-based cell with superior write margin and lower power consumption by about one order of magnitude in comparison with the CMOS-based one. Comparing static noise margin reveals that S-FED-based cells enjoy prominent stability, especially in the read and hold operations with ~3X and 29% improvements, respectively, to the CMOS-based versions. In addition, enhancement of read-stability is attained utilizing S-FED-based cell, as well as decrement of subthreshold current and static power dissipation, compared with the CMOS-based one. Sensitivity analyses extracted from Monte Carlo simulations and butterfly curves indicate that S-FED-based cell successfully tolerates process and supply voltage variations in all operation modes, superior to the CMOS-based counterpart.

Double-Gate Field-Effect Diode: A Novel Device for Improving Digital-and-Analog Performance

In this article, a novel double-gate (DG) field-effect diode (FED) has been proposed, which exhibits smaller short-channel effects (SCEs), smaller OFF-state current ( $I_{\mathrm{\scriptscriptstyle OFF}}$ ) and higher ON-state current ( $I_{\mathrm{\scriptscriptstyle ON}}$ ) compared with the previously introduced common FEDs and the side-contacted FEDs (SFEDs). Based on the TCAD simulation study, due to the stronger control of the two gates over the channel, the proposed double-gate FED (DGFED) is shown to suppress the SCEs and to improve $I_{\mathrm{\scriptscriptstyle ON}}$ / $I_{\mathrm{\scriptscriptstyle OFF}}$ ratio significantly compared with the SFEDs. The proposed device is also shown to have smaller gate delay time, smaller energy-delay product, larger cutoff frequency, and larger transconductance than the SFED. Thus, DGFED is a promising device for substituting the SFED in possible high-frequency analog and digital applications.

Nanoscale field effect diode (FED) with improved speed and I ON / I OFF ratio

Field effect diodes (FEDs) are devices that have higher ON current and lower OFF current compared to metal oxide semiconductor field effect transistors in similar dimensions. The modified FED and side contacted FED (S-FED) structures do not turn off for 40 nm channel lengths and shorter by considering the band-to-band tunnelling model. In this study, a new structure of FED with a 25 nm channel is presented. In this structure, the use of isolating oxides and reservoirs in the channel causes improvement in the structural compared to the conventional FED structures. The proposed techniques reduce the tunnelling in the channel. The simulations have been done by using Silvaco TCAD. In the proposed structure, the results show that the OFF current and gate delay are decreased from 1.5 mA to 66.5 nA and 0.103 to 0.033 ps, respectively. Also, compared with the S-FED structure by considering the band-to-band tunnelling model, the knee voltage for the length of the 25 nm channel dropped from 0.8 to 0.4 volts. Furthermore, the I ON / I OFF ratio, which is an important parameter in digital applications, dramatically increases to a magnitude of 10 5 .

Impact of scaling voltage and size on the performance of Side-contacted Field Effect Diode

Side-contacted Fild Effect Diode (S-FED), with low leakage current and high Ion/Ioff ratio, has been recently introduced to suppress short channel effects in nanoscale regime. The voltage and size scalability of S-FEDs and effects on the power consumption, propagation delay time, and power delay product have been studied in this article. The most attractive properties are related to channel length to channel thickness ratio in the S-FED which reduces in comparison with MOSFET significantly, while gates control over the channel improve and the off-state current reduces dramatically. This promising advantage is not only capable to improve important S-FED's characteristics such as subthreshold slope but also eliminate Latch-up and floating body effect.

Design and Simulation of Low-Power Logic Gates Based on Nanoscale Side-Contacted FED

A new nanoscale device has been already introduced as a side-contacted field effect diode (S-FED), which is composed of a diode and planar SOI-MOSFET. In this paper, S-FED is optimized in terms of work function, with due attention to the design of logic gates, such as NOT, NAND, NOR, and XOR. Results demonstrate that optimum work function is 4.7 eV in which the highest value of $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ can be achieved. Mixed-mode simulations are used to determine the performance of the proposed logic gates. Also, the proof regarding the mitigation of the total power consumption up to 56% is presented so that not gate based on S-FED improves power delay product by about 30%, compared with the CMOS-based version. A similar fabrication process with the CMOS technology could be asserted as the considerable advantage to pave the way of feasibly realizing the new generation of S-FED-based logic gates.

Improving gate delay and I ON/I OFF in nanoscale heterostructure field effect diode (H-FED) by using heavy doped layers in the channel

This paper explores the effects of biaxial tensile strain on the electrical characteristics of the field effect diode (FED) in nanometer regime. The FED current directly depends on carrier mobility in the channel. By employing germanium in the channel, carrier mobility is enhanced and accordingly the derive current is increased. We propose a new structure, namely heterostructure FED (H-FED). The proposed structure does not turn off for channel lengths shorter than 75 nm. We also propose a second new structure called modified H-FED (MH-FFD) to improve the electrical characteristics of H-FED by using the silicon germanium in the source and drain regions, as well as a doped-silicon layer in the channel. Furthermore, we demonstrate that for channel lengths shorter than 40 nm, the side-contacted FED (S-FED) device does not turn off, whereas the proposed structure makes device channel length scaling possible down to 25 nm. The simulation results show that for a 45-nm channel length, the MH-FED gate delay is improved by 40 % and the energy delay product by 35 %, as compared to those of the S-FED. The I ON/I OFF ratio for the MH-FED at channel lengths larger than 60 nm is at least five orders of magnitude higher than that in the S-FED.

Geometrical study of nanoscale field effect diodes

In this paper, the previously proposed side-contacted field effect diode (FED) is carefully studied and its characteristic is compared against that of a modified FED and a metal oxide semiconductor field effect transistor (MOSFET). The influences of the body thickness, each gate length and access resistance are investigated. The figures of merit including intrinsic gate delay time and energy-delay product, which represent the speed and switching energy of the device, respectively, are studied. Our results highlight that FEDs are good candidates for obtaining a high Ion/Ioff ratio with a relatively short delay time compared to conventional FEDs and MOSFETs. We show that by a careful scaling of the source–drain region, the access resistance can be optimized. We demonstrate that a well-tempered device with a high switching response and a lower energy consumption can be achieved with a 30 nm body thickness, 85 nm source–drain length and a drain gate length longer than the source gate length.

Performance Assessment of Nanoscale Field-Effect Diodes

We propose a new structure called a side-contacted field-effect diode (FED). The fabrication of this new structure is simple, and it offers good electrical characteristics. Furthermore, a comprehensive analysis of FEDs is presented. The effect of heavy-doping-induced band-gap narrowing on the performance of FEDs is investigated. Our results show that the calculated <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio is at least two orders of magnitude larger than that obtained from models neglecting this effect. The figures of merit including intrinsic gate delay time, the energy-delay product, and the subthreshold slope have been studied. Our numerical investigations of the scaling of FEDs indicate that, in the nanometer regime, FEDs have a higher <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio. The results demonstrate that FEDs are interesting candidates for future logic applications.