SiC MOS Capacitors Research Articles

Re-Investigation of SiC/SiO<sub>2</sub> Interface Passivation by Nitrogen Annealing

Effect of nitrogen annealing on SiC/SiO2 interface properties was comparatively investigated for SiC MOS capacitors. Interface properties were characterized by normalized parallel conductance and interface state density value, and dielectric strength was evaluated by the electric-field-to-breakdown (Ebd). The results exhibited that both fast and slow states were present at the nitrogen-annealed samples’ parallel conductance characteristics. Thus, we could conclude that nitrogen annealing led to incomplete nitridation of SiC/SiO2 interface. Based on the results, nitridation mechanism was simply analyzed. It seemed that the nitridation process started from near conduction band, extending till to mid-band-gap. Besides, when the samples underwent higher temperature nitrogen annealing, more slow states were converted into fast ones, indicating that higher annealing temperature could lead to more effective nitridation. It was suggested that nitrogen annealing resulted in incomplete nitridation of SiC/SiO2 interface regardless of oxide thickness and that this process was limited to the annealing temperature. The higher the annealing temperature was, the more effective the nitridation effects were.

Oxide trap states versus gas sensing in SiC-MOS capacitors – The effect of N- and P- based post oxidation processes

A novel hydrogen sensor based on Pd/SiO2/SiC capacitors with field oxide ramp termination was fabricated, and a systematic investigation of the most utilized post oxidation annealing (POA) processes, in N or P based ambient, was realized in order to propose the most appropriate technological approach. The experimental structures were electrically characterized, on the one hand to examine the gate oxide quality and, on the other hand, to test the device response as hydrogen sensor. We demonstrated that, whereas the POCl3 based POA leads to significant improvement of the SiO2/SiC interface, and moreover of the oxide breakdown electric field, the 1100°C N2 based POA assures the highest response as hydrogen sensor, both at room temperature and 200°C. Both interface states density and oxide charges present in the MOS structures have been determined and their influence on the observed phenomena have been discussed.

Improvement of SiO<sub>2</sub>/4H-SiC Interface Quality by Post-Oxidation Annealing in N<sub>2</sub> at High-Temperatures

The efficient and practical method for SiO2/4H-SiC interface improvement using post-oxidation annealing (POA) in pure N2 ambient was studied by means of x-ray photoelectron spectroscopy (XPS) analysis and electrical characterization. SiC-MOS capacitors with slope-shaped thermal oxides were used to investigate optimal conditions for interface nitridation. It was found that the amount of nitrogen atoms incorporated into the interfaces increased when raised the annealing temperature up to 1400°C, and thin oxide (< 30 nm) was used. Furthermore, N2-POA at 1400°C was proven to be very promising as equivalent to NO-POA in terms of reduced interface state density of SiC-MOS devices.

Negative Bias Temperature Instability of SiC MOSFET

MOSFETs and MOS capacitors (MOSCAPs) have been fabricated on Si-face of 4H-SiC to investigate the negative bias temperature instability (NBTI) characteristics of SiC MOSFETs. The shifts of threshold voltage of MOSFETs ranged from -216mV to -1257mV after stressed by 1000sec of -1V to -15V gate bias, correspondingly. The negative shift of the threshold voltage indicated that there were positive charges piled up at or near the oxide/SiC interface. In the mean time, the flat-band voltage shifts of SiC MOSCAPs using the same oxide after stressed by -15V bias for 28800 sec at 175°C were negligible, due to insufficient supply of holes, thus suggesting that the NBTI observed in this study was primarily participated by hole trapping, instead of electron emission. The time evolution of DVth induced by negative bias stress was found to saturate quickly, also suggesting that positive charges were primarily coming from trapping of pre-existing near-interface oxide traps, instead of generation of interface traps. The DVth induced by negative bias stress was lower at higher temperature which might be attributed to faster recovery of hole trapping at elevated temperature.

Evaluation method of threshold voltage shift of SiC MOSFETs under negative gate bias using n-type SiC MOS capacitors

A novel method for estimating threshold voltage shifts of n-channel SiC MOSFETs under negative gate bias stresses has been proposed. In the proposed method, n-type SiC MOS capacitors were utilized instead of n-channel SiC MOSFETs. The n-type SiC MOS capacitors were exposed to ultraviolet light to generate holes around the gate region at the SiC surfaces. By applying negative gate voltage under this condition, inversion layers of the holes were formed, and negative gate bias stress was applied to the gate oxides of the n-type SiC MOS capacitors. By this method, we investigated the tendency of flat band voltage shifts in SiC MOS capacitors depending on the gate oxide forming condition, and it was confirmed that the tendency is in accord with that of threshold voltage shifts in SiC MOSFETs obtained by the conventional method.

Quantitative Characterization of Near-Interface Oxide Traps in 4H-SiC MOS Capacitors by Transient Capacitance Measurements

A method to characterize near-interface oxide trap density in SiC MOS capacitors using transient capacitance measurements was investigated, taking account of the distribution of de-trapping time of traps of various locations in oxide. The measurements at room and low temperatures enables us evaluate the responses of the raps of spatially deep and shallow locations, respectively. We found that the sample with low Dit showed smaller density of near-interface traps especially in spatially shallow region in the oxide.

Instability of Critical Electric Field in Gate Oxide Film of Heavy Ion Irradiated SiC MOSFETs

The critical electric field (Ecr) of the gate oxide in 4H-Silicon Carbide (SiC) MOSFETs was measured under inversion bias conditions with ion irradiation. The Linear Energy Transfer (LET) dependence of the Ecr at which the gate oxide breakdown occurred in these MOSFETs was evaluated. The linear relationship between the Ecr-1 and LET was observed for SiC MOSFETs. The slope of the LET-1/Ecr for SiC MOSFETs is almost the same that of the LET-1/Ecr lines for SiC MOS capacitors. The Vds dependence of Ecr was also evaluated. The correlation between the direction of electric field of drain-source region and direction of ion incidence affects to instability of Ecr.

Evaluation of F-N Tunneling Emission Current in MOS Capacitor Fabricated on Step Bunching

This work reports about influence of step bunching of SiC epitaxial-wafer surface on Fowler-Nordheim (F-N) tunneling emission current of SiC-MOS capacitor. We have measured the effective barrier height (ΦB) of SiO2/SiC interface, and estimated the deterioration factor of the effective ΦB on step bunching surface by calculating the local tunneling emission currents. Step bunching fluctuates the gate oxide thickness. The effective ΦB value can be successively derived using our proposed partitioned model in which constant ΦB value of flat surface is used. The fluctuation of the oxide film thickness results in the convergence of F-N tunneling emission currents at the thinner oxide in the MOS capacitor.

Characterization of fast interface states in nitrogen- and phosphorus-treated 4H-SiC MOS capacitors

We investigate ‘fast interface states’ at semiconductor-dielectric interfaces in SiC MOS capacitors that underwent three different interface passivation processes: two nitrogen-based annealing techniques (NO and nitrogen-plasma) and phosphosilicate glass (PSG). ‘Fast interface’ states in this case refer to interface states with response times <1 μs typically used in standard admittance based MOS characterization methods. In order to appropriately characterize the density of interface states (Dit) taking into account these fast states, conductance and high-low frequency C-V methods were used from room temperature down to 100 K. Measuring at lower temperature shifts the response of the fast interface states into the accessible measurement frequency range. The key finding of this work is that while fast interface states were detected in the nitrided samples, such states were not observed in PSG-passivated samples. On the other hand, conventional interface states with time constants similar to those found in silicon samples were detected at room temperature in the PSG samples. The capture cross-section of fast interface states is larger than that of conventional interface states and demonstrates a different energy dependence. These results strongly indicate that the significantly lower density of fast states at the PSG-SiC interface is one of the main reasons for higher channel mobility in PSG MOSFETs.

Single Event Gate Rupture in SiC MOS Capacitors with Different Gate Oxide Thicknesses

The leakage currents through the gate oxide of MOS capacitors fabricated on n-type 4H-Silicon Carbide (SiC) was measured under accumulation bias conditions with heavy-ion irradiation. The Linear Energy Transfer (LET) dependence of the critical electric field (Ecr) at which dielectric breakdown occurred in these capacitors with two different oxide thicknesses was evaluated. The MOS capacitors with thin gate oxide showed higher Ecr values than those with thick gate oxide. The linear relationship between the reciprocal Ecr and LET was observed for both MOS capacitors. The slope of LET dependence of 1/Ecr for SiC MOS capacitors was smaller than that for Si, suggesting that SiC MOS devices are less susceptible to single-event gate rupture (SEGR) than Si MOS devices.

Sub-Bandgap Light-Induced Carrier Generation at Room Temperature in Silicon Carbide MOS Capacitors

Carrier generation characteristics in n-type substrate SiC MOS capacitors induced by sub-bandgap energy light are reported. The generation rate is high enough to create an inversion layer in ~20 minutes with monochromatic light (front side illumination) of energy 2.1 eV in 4H-SiC for electric fields smaller than 1 MV/cm. Generation and recovery results strongly indicate involvement of a metastable defect whose efficiency as a generation center increases under hole-rich and decreases under electron-rich conditions. The generation dependence on bias history and light energy shows the defect to have properties consistent with the metastable silicon vacancy / carbon vacancy-antisite complex (VSi / Vc - CSi).

Synchrotron Radiation Photoelectron Spectroscopy Study of Thermally Grown Oxides on 4H-SiC(0001) Si-Face and (000-1) C-Face Substrates

The fundamental aspects of thermal oxidation and oxide interface grown on 4H-SiC(0001) Si-face and (000-1) C-face substrates were investigated by means of high-resolution x-ray photoelectron spectroscopy (XPS) using synchrotron radiation together with electrical measurements of SiC-MOS capacitors. We found that, for both cases, there existed no distinct C-rich transition layer despite the literature. In contrast, atomic scale roughness causing degradation of SiC-MOS devices, such as negative fixed charge and electrical defects just at the oxide interface, was found to be introduced as thermal oxidation progressed, especially for the (000-1) C-face substrate.

Investigation of gate edge effect on interface trap density in 3C–SiC MOS capacitors

Abstract This paper reports on investigation of the gate edge effect on the interface trap density characteristics of 3C–SiC MOS capacitors fabricated using four different gate materials and two SiO 2 oxide preparation methods. Non-uniform distribution of interface trap densities under the gate was demonstrated by the presence of the gate edge effect, i.e. the dependence of D it ( E ) on the ratio of gate perimeter to its area. The strength of the gate effect in different gate/oxide material combinations was studied and it was found that it depends on gate thermal expansion coefficient and adhesion of the gate layer to the oxide layer. The D it behaviour at shallow energy levels (0.25 eV) was attributed to the reaction of P b -centres to mechanical stress. The behaviour of D it at deeper levels was documented but could not be explained in this study.

Oxygen Ion Induced Charge in SiC MOS Capacitors Irradiated with Gamma-Rays

Charge induced in 6H-SiC nMOS capacitors by 15 MeV oxygen ion microbeams was measured using Transient Ion Beam Induced Current (TIBIC) before and after gamma-ray irradiations. The peak amplitude of TIBIC signals decreases and the fall time increases with increasing number of incident ions. The decrease in the TIBIC peak eventually saturated. The TIBIC signal can be refreshed to its original shape by applying a positive bias of + 1V to gate oxide. Small decrease in both the peak amplitude of TIBIC signal and collected charge was observed due to gamma-ray irradiation.

Experimental Identification of Extra Type of Charges at SiO&lt;sub&gt;2&lt;/sub&gt;/SiC Interface in 4H-SiC

High temperature C-V characterization with and without UV illumination has been performed on n-type 4H-SiC MOS capacitors fabricated using different processing conditions to extract various types of interfacial charges. An anomalous positive flatband voltage shift with temperature has been observed in most of the SiC MOS capacitors measured. We have experimentally identified an extra type of fixed charges at the 4H-SiC/SiO2 interface from the temperature dependence of the flatband voltage, particularly under UV illumination.

N 2 O -grown oxides/4H-SiC (0001), (033¯8), and (112¯) interface properties characterized by using p-type gate-controlled diodes

The N2O-grown SiO2/4H-SiC (0001), (033¯8), and (112¯0) interface properties in p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) have been characterized by using gate-controlled diodes. Although the inversion layer is not formed in simple SiC MOS capacitors at room temperature due to its large bandgap, a standard low frequency capacitance-voltage (C-V) curve can be obtained for the gate-controlled diodes, owing to the supply of minority carriers from the source region. From the quasistatic C-V curves measured by using gate-controlled diodes, the interface state density has been evaluated by an original method proposed in this study. The interface state density near the valence band edge evaluated by the method is the lowest at the oxides/4H-SiC (033¯8) interface. Comparison with the channel mobility is also discussed.

Influence of TCE concentration in thermal oxidation on reliability of SiC MOS capacitors under Fowler–Nordheim electron injection

The effects of trichloroethylene (TCE) concentration in SiC thermal oxidation on the reliability of MOS capacitors under Fowler–Nordheim (FN) electron injection have been investigated. It is found that TCE thermal oxidation can enhance the resistance of the SiO 2/SiC interface against generation of interface states and oxide charges caused by FN electron injection, and the resistance increases with TCE ratio increasing from 0 to 0.1. As compared with the control sample based on dry-O 2 oxidation, the interface-state generation at 0.25 eV below the conduction-band edge is 5, 23, and 170 times smaller for samples with TCE ratio of 0.01, 0.05 and 0.1 respectively. In addition, the interface traps and oxide-charge traps of fresh samples decrease with increasing TCE ratio for the ratio less than 0.01, and then increase for larger ratio. It is proposed that the enhanced resistance against the stress is attributed to the gettering or dislodging of electrical and physical defects by the chlorine atoms incorporated in the oxide during the TCE oxidation.

Time-Dependent Bias Stress-Induced Instability of SiC MOS Devices

AbstractWe have observed a gate-bias stress induced instability in both the threshold voltage of SiC MOSFETs and the flatband voltage of SiC MOS capacitors. The magnitude of this bias stress-induced instability generally increases linearly with log time, with no saturation of the effect observed, even out to 100,000 seconds. The magnitude also increases with increasing gate field. A positive gate-bias stress causes a positive shift and a negative gate-bias stress causes a negative shift, consistent with electron tunneling into or out of oxide traps near the SiC / SiO2 interface as opposed to mobile ions drifting across the gate oxide. The effect is repeatable.

Defect-engineering in SiC by ion implantation and electron irradiation

Three examples are given, which show that ion implantation and electron irradiation can drastically modify the electrical properties of SiC and SiC-based MOS capacitors. (1) It is demonstrated that sulphur ions (S +) implanted into 6H-SiC act as double donors with ground states ranging from 310 to 635 meV below the conduction bandedge. (2) Co-implantation of nitrogen (N +) – and silicon (Si +) – ions into 4H-SiC leads to a strong deactivation of N donors. Additional experiments with electron (e −)-irradiated 4H-SiC samples ( E(e −) = 200 keV) support the idea that this deactivation is due to the formation of an electrically neutral ( N x – V C, y )-complex. (3) Implantation of a surface-near Gaussian profile into n-type 4H-SiC followed by a standard oxidation process leads to a strong reduction of the density of interface traps D it close to the conduction bandedge in n-type 4H-SiC/SiO 2 MOS capacitors.

Comparison of charge–retention times in n- and p-type 4H–SiC MOS capacitors as non-volatile memory elements

Retention of non-equilibrium charge in MOS capacitors on p-type 4H SiC with thermally grown nitrided gate oxides have been experimentally investigated. The reasons of short charge–retention time in this type of capacitors compared to n-type MOS capacitors have been identified: supply of minority carriers from the perimeter of the capacitors contributes to fast creation of the inversion layer. A negatively biased shielding ring has been employed to eliminate the lateral supply of minority carriers (electrons) and to enable measurement of the effective generation rate.