SiC Metal-oxide-semiconductor Field-effect Transistors Research Articles

Annealing influence on stoichiometry and band alignment of 4H-SiC/SiO2 interface evaluated by x-ray photoelectron spectroscopy

Abstract Post oxidation annealing (POA) is a crucial technique for enhancing the performance of SiC Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs). This study investigates the impact of nitrogen-based POA on the 4H-SiC/SiO2 interface, utilizing X-ray photoelectron spectroscopy (XPS) to assess changes in stoichiometry and band alignment. We discovered that high-temperature nitrogen POA significantly refines the interface quality, shifting the SiOxCy binding energy from 101.3 eV (at 400°C) to 102.1 eV (at 1150°C) and reducing the C:Si ratio from 1.120 (at 400°C) to 0.972 (at 1150°C), indicating reoxidation and transition from C-rich interface to Si-rich interface. Despite improvements, the conduction band offset at the interface, decreases from 2.59 eV to 1.62 eV with increasing annealing temperature, suggesting a higher likelihood of electron tunneling. This finding underscores the necessity of evaluating band offsets introduced by POA to ensure the reliability of SiC MOSFETs. Additionally, excessive Ar ion etching introduces residual Ar and surface charges, causing band bending and an increased density of states in the valence band of the 4H-SiC substrate.

Al–O–Al defect complexes as possible candidates for channel electron mobility reducing trapping centers in 4H-SiC metal–oxide–semiconductor field-effect transistors

The deep-level drain current transient spectroscopy (Id-DLTS) measurements of Al-doped SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) strongly suggest that the reduction in the channel mobility at low temperatures is related to a shallow trap detectable at 70 K. Using the Shockley–Reed–Hall (SRH) theory, the level of this trap has been extracted to be around 0.15 eV below the conduction band minimum of SiC. Density functional theory (DFT) calculations of AlSiNCAlSi and AlSiOCAlSi defect complexes have found one configuration of the AlSiOCAlSi complex, which has a charge transition level within the SRH extracted trap level range. Therefore, we suggest that these AlSiOCAlSi defects are likely candidates for traps responsible for the channel mobility reduction.

Effect Evaluation and Modeling of p-Type Contact and p-Well Sheet Resistance of SiC MOSFET with Respect to Switching Characteristics

SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) exhibit excellent high-speed switching characteristics. However, the sheet resistance of the p-body region and the contact resistance between the p-body region and source electrode significantly degrade the switching performance. In this study, to clarify the effect of resistance on switching speed, which has not been sufficiently explored before, we used the temperature dependence of sheet and contact resistance and conducted switching tests under different temperature conditions. Furthermore, we created a circuit model that considered body effects and compared the results of the models with the measurements. We were able to reproduce the same temperature and resistance dependences as those exhibited by the experimental results, thus confirming the effectiveness of the model.

Comparison of Si and SiC MOSFETs responses to electrical stress and the observation of parameter recovery in SiC MOSFET by stress superposition

In this study we examined the effects of room temperature DC and AC electrical stress on Si and SiC n-channel metal-oxide-semiconductor field effect transistors (MOSFETs). Measurement of threshold voltage, transconductance, subthreshold swing, charge pumping, and gate oxide breakdown are used to compare the impact of stress on Si MOSFETs and SiC MOSFETS, as well as to understand the processes of carrier injection and trapping at oxide and interface defects. DC stress is observed to promote negative charge buildup in the gate oxide and interface in Si MOSFETs. However, in SiC MOSFETs the net charge buildup sign alternates between negative and positive as the DC stress polarity is changed from positive to negative, respectively. For the same stress level, relative degradation in parameters of SiC MOSFETs are significantly smaller than those in Si MOSFETs, where in the latter interface state density, conductance, and subthreshold swing have degraded by up to 400%.The change of charge buildup sign explains our observation that degradation in SiC MOSFETs subjected to AC bipolar stress is insignificantly small, whereas AC stressing of Si MOSFETs is observed to be much more severe. Also, the superposition of alternating DC stress polarity eliminates the stress induced degradation in SiC MOSFETs thus enabling a straightforward process for parameter reconfiguration and recovery.

A Novel Deep-Trench Super-Junction SiC MOSFET with Improved Specific On-Resistance.

In this paper, a novel 4H-SiC deep-trench super-junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a split-gate is proposed and theoretically verified by Sentaurus TCAD simulations. A deep trench filled with P-poly-Si combined with the P-SiC region leads to a charge balance effect. Instead of a full-SiC P region in conventional super-junction MOSFET, this new structure reduces the P region in a super-junction MOSFET, thus helping to lower the specific on-resistance. As a result, the figure of merit (FoM, BV2/Ron,sp) of the proposed new structure is 642% and 39.65% higher than the C-MOS and the SJ-MOS, respectively.

An investigation into the short-circuit characteristics of Sic MOSFET power devices

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) devices exhibit substantial prospects for application under extreme operational conditions, including elevated temperatures, high voltages, and high frequencies. Nevertheless, owing to their distinctive material and structural attributes, SiC MOSFET devices are not devoid of challenges, with the short-circuit phenomenon constituting a pivotal avenue of inquiry. The short-circuit effect pertains to the abrupt escalation of leakage current that these devices might undergo under elevated voltage conditions, thereby exerting a perturbing influence on their stability and reliability. Investigations into the short-circuit effect predominantly revolve around two dimensions: one involves comprehending its underlying physical mechanisms, while the other centers on identifying commensurate remedial approaches.With respect to the underlying physical mechanisms, researchers have discerned that the elevated breakdown field strength and augmented carrier mobility intrinsic to SiC materials engender an augmentation in leakage current, consequently giving rise to the short-circuit effect. Furthermore, factors such as oxide layer anomalies and surface states are also conceivable catalysts for the surge in leakage current. To rectify this predicament, scholars have proffered a panoply of stratagems, encompassing the optimization of material synthesis processes, enhancement of oxide layer quality, refinement of device structural designs, and incorporation of protective circuitry, among others. In summation, the investigation of the short-circuit effect in silicon carbide MOSFET devices is fundamentally aimed at attaining an in-depth comprehension of its causative mechanisms. Moreover, it endeavors to proffer efficacious resolutions conducive to augmenting the reliability and steadfastness of these devices within high-temperature and high-voltage environments, thereby facilitating their widespread integration within the ambit of high-performance power electronics.

Carrier injection induced degradation of nitrogen passivated SiC–SiO2 interface simulated by time-dependent density functional theory

The performance of SiC-based metal-oxide-semiconductor field-effect transistors (MOSFETs) degrades seriously after a period of continuous operation. To directly understand this issue, we conduct real-time time-dependent density functional theory (TDDFT) simulations on a series of nitrogen passivated SiC–SiO2 interfaces to monitor the interaction between carriers and interface atoms. We find that the nitrogen passivation always leaves behind two local states near the VBM, which gives a chance to the strong interaction between channel carriers and C–N bonds, and finally results in the generation of C dangling bond defects. These processes are vividly presented and confirmed by the TDDFT simulation. Additionally, the results show that the new defects are more easily formed by the passivated C cluster than the passivated Si vacancy. These studies provide physical insights into the degradation mechanisms of working SiC MOSFETs, while simultaneously demonstrating the advantage of TDDFT as a crucial tool for investigating defect generation dynamics in semiconductor devices.

Mechanisms of negative bias instability of commercial SiC MOSFETs observed by current transients

This article explains the mechanisms of negative bias instability in commercial n-channel SiC metal–oxide semiconductor field-effect transistors (MOSFETs) by analysis of transient gate currents. The current–voltage measurements were performed at different temperatures along with capacitance–voltage measurements to characterise hole trapping and de-trapping in planar SiC MOSFETs. The experimental results reveal that near-interface traps (NITs) with energy levels aligned to the valence band trap holes from the valence band by tunneling, which is different from published results about NITs with energy levels aligned to the energy gap. The impact of the aluminium implantation process of the p-type region on hole trapping is also demonstrated. The presented analysis also reveals that the hole trapping by NITs is limited to the p-type region, indicating that the aluminium implantation process is responsible for the detected NITs.

Heavy ion single event effect in double-trench SiC metal–oxide–semiconductor field-effect transistors

In this paper, experiments on 208 MeV Ge ion irradiation with different source-drain bias voltages are carried out for the double-trench SiC metal–oxide–semiconductor field-effect transistors, and the physical mechanism of the single event effect is analyzed. The experimental results show that the drain leakage current of the device increases more obviously with the increase of the initial bias voltage during irradiation. When the bias voltage is 400 V during irradiation, the device has a single event burned at a fluence of 9×10<sup>4</sup> ion/cm<sup>2</sup>, and when the bias voltage is 500 V, the device has a single event burned at a fluence of 3×10<sup>4</sup> ion/cm<sup>2</sup>, so when the LET value is 37.3 MeV·cm<sup>2</sup>/mg, the SEB threshold of DUT does not exceed 400 V, which is lower than 34 % of the rated operational voltage. The post gate-characteristics test results show that the leakage current of the device with a bias voltage of 100 V does not change significantly during irradiation. When the bias voltage is 200 V, the gate leakage and the drain leakage of the device both increase, so do they when the bias voltage is 300 V, which is positively related to bias voltage. In order to further analyze the single particle effect mechanism of device, the simulation is conducted by using TCAD tool. The simulation results show that at low bias voltage, the heavy ion incident device generates electron-hole pairs, the electrons are quickly swept out, and the holes accumulate at the gate oxygen corner under the effect of the electric field, which combines the source-drain bias voltage, leading to the formation of leakage current channels in the gate oxygen layer. The simulation results also show that at high bias voltage, the electrons generated by the incident heavy ion move towards the junction of the N<sup>–</sup> drift layer and the N<sup>+</sup> substrate under the effect of the electric field, which further increases the electric field strength and causes significant impact ionization. The local high current density generated by the impact ionization and the load large electric field causes the lattice temperature to exceed the melting point of silicon carbide, causing single event burnout. This work provides a reference and support for studying the radiation effect mechanism and putting silicon carbide power devices into aerospace applications.

Circuit simulation-based comparison of power electronics devices in a five-level converter for UAV applications

<p>In this paper, the performance of a 5-level cascaded H-bridge inverter in unmanned aerial vehicle (UAV) applications is analized to identify, at the converter design stage, the better device choice depending on different UAV operation scenarios. Considering that regardless of the specific application there are some typical operations, such as take-off, climb, land, cruise, and potential recurring climbs and descents, the results can support the choice by considering the typical working conditions of the specific application where the UAV would be used. The results have been obtained by simulating the H-bridge inverter considering the circuit models of insulated-gate bipolar transistors (IGBTs), GaN high-electron-mobility transistors (HEMTs), and Si and SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) provided by manufacturers. The study has highlighted that the choice of the device depends on the UAV usage, switching frequency, and load conditions. More specifically, considering the typical devices and systems costs in the case of a selective harmonic elimination procedure operating at the fundamental switching frequency, the Si devices should be used. Moreover, the preference for using IGBTs or Si MOSFETs depends on the typical working conditions of the UAV application. In the case of phase-shift carrier modulation technique, at 4 kHz the MOSFET is the best device and the choice between Si and SiC devices depends on the UAV application's main operation scenarios. At 20 kHz the SiC MOSFET is the best device, while at higher frequencies the GaN HEMT cost should be faced to take advantage of its best performance.</p>

Observations of very fast electron traps at SiC/high-κ dielectric interfaces

Very fast interface traps have recently been suggested to be the main cause behind poor channel-carrier mobility in SiC metal–oxide–semiconductor field effect transistors. It has been hypothesized that the NI traps are defects located inside the SiO2 dielectric with energy levels close to the SiC conduction band edge and the observed conductance spectroscopy signal is a result of electron tunneling to and from these defects. Using aluminum nitride and aluminum oxide as gate dielectrics instead of SiO2, we detect NI traps at these SiC/dielectric interfaces as well. A detailed investigation of the NI trap density and behavior as a function of temperature is presented and discussed. Advanced scanning transmission electron microscopy in combination with electron energy loss spectroscopy reveals no SiO2 at the interfaces. This strongly suggests that the NI traps are related to the surface region of the SiC rather than being a property of the gate dielectric.

Low working loss Si/4H–SiC heterojunction MOSFET with analysis of the gate-controlled tunneling effect

A silicon (Si)/silicon carbide (4H–SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based on simulations. In this structure, the channel regions are made of Si to take advantage of its high channel mobility and carrier density. The voltage-withstanding region is made of 4H–SiC so that HDT-MOS has a high breakdown voltage (BV) similar to pure 4H–SiC double-trench MOSFETs (DT-MOSs). The gate-controlled tunneling effect indicates that the gate voltage (VG) has a remarkable influence on the tunneling current of the heterojunction. The accumulation layer formed with positive VG can reduce the width of the Si/SiC heterointerface barrier, similar to the heavily doped region in an Ohmic contact. This narrower barrier is easier for electrons to tunnel through, resulting in a lower heterointerface resistance. Thus, with similar BV (approximately 1770 ​V), the specific on-state resistance (RON-SP) of HDT-MOS is reduced by 0.77 ​mΩ‧cm2 compared with that of DT-MOS. The gate-to-drain charge (QGD) and switching loss of HDT-MOS are 52.14 ​% and 22.59 ​% lower than those of DT-MOS, respectively, due to the lower gate platform voltage (VGP) and the corresponding smaller variation (ΔVGP). The figure of merit (QGD ​× ​RON-SP) of HDT-MOS decreases by 61.25 ​%. Moreover, the heterointerface charges can reduce RON-SP of HDT-MOS due to trap-assisted tunneling while the heterointerface traps show the opposite effect. Therefore, the HDT-MOS structure can significantly reduce the working loss of SiC MOSFET, leading to a lower temperature rise when the devices are applied in the system.

Factors Affecting Bias Temperature Instability in 4H-SiC MOS Capacitors

The threshold voltage of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) show instability during normal operation, especially after bias temperature stress (BTS), and this phenomenon is called bias temperature instability (BTI). In this work, to study the factors affecting threshold voltage (Vth) instability of SiC MOSFETs, flat-band voltage (Vfb) instability of 4H-SiC metal-oxide-semiconductor (MOS) capacitors is discussed instead. Some factors, including the polarity of gate bias stress, stress time, and stress temperature, are analyzed by performing one-way bias stress C-V measurements in the devices. Firstly, positive bias stress leads to a positive Vfb shift, and negative bias stress leads to a negative one. Moreover, the Vfb shift appears to exhibit a linear relationship with log (stress time). Furthermore, the Vfb shift decreases over the temperature range of 225 K to 400 K, but slightly increases at 475 K. Finally, the Vfb stability of the MOS devices fabricated by 1200 °C NO post-oxidation annealing (POA) and those fabricated by 1250 °C NO POA is similar.

Comparison of the Performance-Degrading Near-Interface Traps in Commercial SiC MOSFETs

This paper presents a comparison of the density of performance-degrading near-interface traps (NITs) in the most commonly available 1200 V commercial N-channel SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). A recently developed integrated-charge technique was used to measure the density of NITs with energy levels aligned to the conduction band, which degrade MOSFET’s performance by capturing and releasing electrons from the channel biased in the strong-inversion condition. Trench MOSFETs of one manufacturer have lower densities of these NITs in comparison to MOSFETs with the planar gate structure, corresponding to observed higher channel-carrier mobility in trench MOSFETs. Different response-time distributions were also observed, corresponding to different spatial location of the measured NITs.

Trap Characterization of Trench-Gate SiC MOSFETs Based on Transient Drain Current

The SiC/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface state is one of the main factors that limit the performance and reliability of the SiC metal-oxide-semiconductor field-effect transistor (MOSFET). In this paper, we use a Bayesian deconvolution algorithm to optimize trap feature extraction based on the transient current method and improve the trap extraction accuracy. Using this method, we study the trap capture mechanism in SiC MOSFETs and mainly characterize the trap position, the trap energy level, and the capture time constant. The results obtained show that there are three different types of traps and defects, two of which are SiC interface traps at the gate-source and gate-drain interfaces, with activation energies of 0.089 eV and 0.035 eV, respectively; the third trap type is an oxide trap, and its time constant does not vary with temperature. The characterization results are verified via deep level transient spectroscopy, and the results show reasonable agreement with those obtained by the method proposed in this paper. This method can be combined with electrical stress testing in long-term reliability research to realize nondestructive characterization of the defects of SiC MOSFETs.

Radiation damage in GaN/AlGaN and SiC electronic and photonic devices

The wide bandgap semiconductors SiC and GaN are commercialized for power electronics and for visible to UV light-emitting diodes in the case of the GaN/InGaN/AlGaN materials system. For power electronics applications, SiC MOSFETs (metal–oxide–semiconductor field effect transistors) and rectifiers and GaN/AlGaN HEMTs and vertical rectifiers provide more efficient switching at high-power levels than do Si devices and are now being used in electric vehicles and their charging infrastructure. These devices also have applications in more electric aircraft and space missions where high temperatures and extreme environments are involved. In this review, their inherent radiation hardness, defined as the tolerance to total doses, is compared to Si devices. This is higher for the wide bandgap semiconductors, due in part to their larger threshold energies for creating defects (atomic bond strength) and more importantly due to their high rates of defect recombination. However, it is now increasingly recognized that heavy-ion-induced catastrophic single-event burnout in SiC and GaN power devices commonly occurs at voltages ∼50% of the rated values. The onset of ion-induced leakage occurs above critical power dissipation within the epitaxial regions at high linear energy transfer rates and high applied biases. The amount of power dissipated along the ion track determines the extent of the leakage current degradation. The net result is the carriers produced along the ion track undergo impact ionization and thermal runaway. Light-emitting devices do not suffer from this mechanism since they are forward-biased. Strain has also recently been identified as a parameter that affects radiation susceptibility of the wide bandgap devices.

Electrically Active Defects in SiC Power MOSFETs

The performance and reliability of the state-of-the-art power 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) are affected by electrically active defects at and near the interface between SiC and the gate dielectric. Specifically, these defects impact the channel-carrier mobility and threshold voltage of SiC MOSFETs, depending on their physical location and energy levels. To characterize these defects, techniques have evolved from those used for Si devices to techniques exclusively designed for the SiC MOS structure and SiC MOSFETs. This paper reviews the electrically active defects at and near the interface between SiC and the gate dielectric in SiC power MOSFETs and MOS capacitors. First, the defects are classified according to their physical locations and energy positions into (1) interface traps, (2) near interface traps with energy levels aligned to the energy gap, and (3) near-interface traps with energy levels aligned to the conduction band of SiC. Then, representative published results are shown and discussed for each class of defect.

Recent Advances in Short Circuit Protection Methods for SiC MOSFET

Due to its high efficiency, low switching losses, and high temperature stability, Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has been widely used in various fields. Therefore, the protection of SIC MOSFET devices is crucial. The significance of this research topic lies in comparing the existing short-circuit protection methods and technologies for SiC MOSFET, pointing out the advantages and shortcomings of each method, and providing suggestions. Firstly, the principles and impacts of HSF and FUL in short-circuit faults are introduced. Secondly, this article elaborates on shortcircuit protection methods from two aspects: hardware protection and software protection, concentrating mostly on recently researched hardware protection methods. Finally, a comparison between the two protection methods is made, and potential improvement solutions are proposed. Based on the research conducted, the author believes that the current hardware protection method based on current detection is the optimal solution for SiC MOSFET short-circuit protection. Future research can be focused on integrating other solutions for further optimization on this basis.

Heavy ion single event effect in double-trench SiC metal-oxide-semiconductor field-effect transistors

In this paper, experiments on 208 MeV Ge ion irradiation with different source-drain bias voltages are carried out for the double-trench SiC metal–oxide–semiconductor field-effect transistors, and the physical mechanism of the single event effect is analyzed. The experimental results show that the drain leakage current of the device increases more obviously with the increase of the initial bias voltage during irradiation. When the bias voltage is 400 V during irradiation, the device has a single event burned at a fluence of 9×10&lt;sup&gt;4&lt;/sup&gt; ion/cm&lt;sup&gt;2&lt;/sup&gt;, and when the bias voltage is 500 V, the device has a single event burned at a fluence of 3×10&lt;sup&gt;4&lt;/sup&gt; ion/cm&lt;sup&gt;2&lt;/sup&gt;, so when the LET value is 37.3 MeV·cm&lt;sup&gt;2&lt;/sup&gt;/mg, the SEB threshold of DUT does not exceed 400 V, which is lower than 34% of the rated operational voltage. The post gate-characteristics test results show that the leakage current of the device with a bias voltage of 100 V does not change significantly during irradiation. When the bias voltage is 200 V, the gate leakage and the drain leakage of the device both increase, so do they when the bias voltage is 300 V, which is positively related to bias voltage. In order to further analyze the single particle effect mechanism of device, the simulation is conducted by using TCAD tool. The simulation results show that at low bias voltage, the heavy ion incident device generates electron-hole pairs, the electrons are quickly swept out, and the holes accumulate at the gate oxygen corner under the effect of the electric field, which combines the source-drain bias voltage, leading to the formation of leakage current channels in the gate oxygen layer. The simulation results also show that at high bias voltage, the electrons generated by the incident heavy ion move towards the junction of the N&lt;sup&gt;–&lt;/sup&gt; drift layer and the N&lt;sup&gt;+&lt;/sup&gt; substrate under the effect of the electric field, which further increases the electric field strength and causes significant impact ionization. The local high current density generated by the impact ionization and the load large electric field causes the lattice temperature to exceed the melting point of silicon carbide, causing single event burnout. This work provides a reference and support for studying the radiation effect mechanism and putting silicon carbide power devices into aerospace applications.

A novel high‐voltage solid‐state switch based on the SiC MOSFET series and its overcurrent protection

AbstractAll‐solid‐state switches are one of the core components of pulsed power supply systems. However, the voltage level of a single switch is limited. By optimizing the chip structure, the voltage level of a single switch can be improved. Due to the immaturity of the production process and the positive correlation between the blocking voltage and the on‐resistance of the switch, it is difficult to improve the blocking voltage and the continuous forward current of a single switch simultaneously. The series‐connected switch is a way to increase the switch's blocking voltage without reducing the switch's continuous forward current. Magnetically coupled isolated drive and resistor‐capacitor forced voltage equalization techniques are investigated to increase the blocking voltage of the switches using multiple SiC metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) in series connections. Meanwhile, a special overcurrent protection scheme is designed to improve the reliability of the series‐connected switch. Finally, a high‐voltage solid‐state switch is developed based on the SiC MOSFET series connections, whose output pulse width is adjustable from 20 to 300 μs, frequency is adjustable from 1 Hz to 3 kHz, the maximum output voltage can reach 57 kV (1 Hz), and the overcurrent protection time is about 1 μs.