SiC Chip Research Articles

Scalable Core Package for Power Module with Double-Sided Cooling Capability Applying Fan-out Panel-Level Process Suitable for SiC and GaN

Recently, as the demand for electric vehicles, charging infrastructure and renewable energy grows in response to the need for energy conservation and a low-carbon society, there has been growing interest in the development of SiC, which offers advantages in high-temperature operation, high-speed operation and low ON-resistance. SiC is expected to have lower heat loss and higher switching conversion efficiency. Several SiC inverter modules (packaging) have been proposed, but further concept development is needed in terms of size/thickness, heat dissipation characteristics, parasitic resistance and inductance. In this report, we propose a thinner, smaller and higher heat dissipation SiC core module package with double-sided cooling capability by applying Fan-Out panel level process. The package internal wiring consists of Cu Via and large-area fan-out RDL, enabling high heat dissipation, low resistance and low inductance. These have the advantage of maintaining surge voltages equivalent to those of Si and also reducing current variations between SiC chips, which also allows for fast switching. On the other hand, SiC crystals are harder than Si crystals (about 3 times), so the compressive stress on the chip is greater, requiring less stress and less warpage at the package level. We have confirmed by thermal stress simulations that stress and warpage reduction can be achieved by applying EMC materials with high Tg but very low Young’s modulus. In this report, we report the results of verification by simulation and actual prototypes in terms of heat dissipation and thermal stress.

The improvement of heat transfer using Co/SiO2 spiral structured catalyst for green diesel production by Fischer–Tropsch synthesis

In this study, the improvement of heat transfer was applied to eliminate hotspots of a highly exothermic reaction, Fischer–Tropsch synthesis (FTS), by means of two facile methods: (I) adding high thermal conductive materials media diluted in catalysts (SiC and Al chips), and (II) using structured reactors equipped with well-designed structured catalysts with advantages of heat dissipation/removal. The 20%Co/SiO2 catalyst powder prepared by simple impregnation was employed for constructing structured catalysts and granular packed bed catalysts. The structured catalyst was prepared by coating method of Co/SiO2 slurry on an aluminum spiral and plate substrate. The catalytic performance of as-prepared catalysts was then tested for FTS in a fixed-bed reactor at 210–230 °C, 20 bar. Both gaseous and liquid products were collected and analyzed. The heat transfer improvement of packed bed catalytic system and structured catalytic system were compared and discussed. As a result, the structured catalytic system with spiral structured catalyst can provide the best improvement of heat/mass transfer, resulting in enhanced diesel selectivity, though the oil production rate was unsatisfactory. Meanwhile, among the packed bed catalytic systems, SiC media possessed the best heat removal material, producing the highest oil yield. In addition, the fresh and spent catalysts were analyzed by several techniques including TEM, SEM, XRD, BET, ICP-OES, H2–TPR, and TGA to relate the physicochemical properties of the prepared catalysts and its FTS performance.

The effect of wafer thinning and thermal capacitance on chip temperature of SiC Schottky diodes during surge currents

Due to superior material properties of SiC for high-voltage devices, SiC Schottky diodes are used in energy-conversion systems such as solar-cell inverters, battery chargers, and power modules for electric cars and unmanned aerial vehicles. The reliable operation of these systems requires the chip temperature of SiC Schottky diodes to be maintained within the limit set by the device package. This is especially crucial during surge-current events that dissipate heat within the device. As a thermal-management method, manufactures of commercial SiC Schottky diodes have introduced wafer thinning practices to reduce the thickness of the SiC chip and, consequently, to reduce its thermal resistance. However, this also leads to a reduction in the thermal capacitance. In this paper, we present experimental data and theoretical analysis to demonstrate that the reduced thermal capacitance has a much larger adverse effect in comparison to the beneficial reduction of the thermal resistance. An implication of the presented results is that, contrary to the adopted wafer thinning practices, SiC Schottky diodes fabricated without wafer thinning have superior surge-current capability.

Growth of Cu nanotwinned films on surface activated SiC chips

Growth of Cu nanotwinned films on surface activated SiC chips

Low-Temperature Die Bonding of SiC Chips with DBC Ceramic Substrates Using High-Density Ag (111) Nanotwinned Films

Low-Temperature Die Bonding of SiC Chips with DBC Ceramic Substrates Using High-Density Ag (111) Nanotwinned Films

The Mechanisms of Oxygen Accelerated Low‐Temperature Bonding by Ag Nanoparticles

AbstractLow‐temperature bonding (≤300 o C) using Ag nanoparticles (Ag NPs) is considered to be the new generation of bonding technology in power electronics. The oxygen‐accelerated sintering has been observed by many researchers which is attributed to the decomposition of organics covered on Ag NPs. In this work, organic‐free Ag NPs are fabricated to eliminate the influence of organics, and it is found that the accelerated bonding process by oxygen is strongly correlated to the self‐confined amorphous Ag‐O compound shell on the surface of Ag NPs. In experiments, the sintering process is apparently accelerated by the elevating oxygen content, and the amorphous shell is observed after sintering, which do not grow thicker even in pure oxygen ambient for a long time while performing active chemical evolutions. In simulations, the results match well with the experiments and indicate that the amorphous shell performed the dynamic oxidation and decomposition process. This dynamic equilibrium is caused by the instability of silver oxides, which would enable the amorphous shell to activate the mobility of the surface mass flow and promote the surface diffusion. The shear strength of SiC chip increased by 354% when bonding in pure oxygen, targeting a broad variety of applications in electronic packaging.

Formation mechanism, interface characteristics and the application of metal/SiC thin-film ohmic contact after high-temperature treatment

SiC, as a representative of the third generation semiconductors, is widely investigated in power devices and sensors. However, ohmic contacts, an important component for signal output of various SiC chips, have always faced challenges with unclear formation mechanism and difficulty to withstand high temperature. To solve such problems, two sets of NPN-type SiC ohmic contact were prepared, including Ti/TaSi2/Pt and Ni/W. Experimental results show that whether ohmic contact can be formed mainly depends on the contact metal. The alloy phase with lower work function is formed after high temperature annealing, which reduces the height and width of the Schottky barrier. For the prepared SiC ohmic contacts, It was demonstrated that the invasion of oxygen atoms cause contacts failure, and incorporation of barrier layer (Ta-based layer) and effective protective layer (Pt layer) determine whether high temperatures can be tolerated. Finally, piezoresistive 4H–SiC pressure sensor chips with dimensions of 3000 μm × 3000 μm × 200 μm were fabricated using the obtained ohmic contacts. Sensor chips output resistance were monitored up to 600 °C in air to show stability of the ohmic contact. The highly stable and high temperature ohmic contact can be applied in a variety of SiC devices.

Geometry Optimization for Increasing Fatigue Life of Pressing Packaged IGBT with SiC Chips and Silver Sintering Layers

A novel SiC IGBT module packaging structure is proposed. Pressing packaging with silver sintering is adopted. The thermal analysis is made with FEM. A maximum temperature of 137°C is obtained when the module is working, which leads to significant fatigue problem. The minimum fatigue life of the fundamental model is 106, and it occurs in the upper silver layer nearby the SiC. Five improved models with different silver layer edge geometry are analyzed. It turns out that the best geometry optimization in this study can lead to a fatigue life of 141, that is, 33% higher than the fundamental model. This shows that a very subtle change in the geometry of the silver layer edge can lead to significant improvement of the fatigue life of the module. This result can provide useful reference for the design the third generation IGBT device.

Displacement damage and single event effects of SiC diodes and MOSFETs by neutron, heavy ions and pulsed laser

SiC diodes and MOSFETs (device under test, DUTs) have been tested by neutron and heavy ions, pulsed laser separately or both. Neutron displacement damage (DD) results show that up to 1E12/cm2 neutrons there is no significant leakage current increasing; DUTs have been tested by heavy ion and pulsed laser to get their single event burnt-out (SEB) threshold at some working voltages, results show that pulsed laser and heavy ion are consistent with each other. Then one of the diodes and MOSFETs which has been tested by neutron was tested by pulsed laser to get SEB laser energy threshold, results show after neutron test SEB threshold laser energies will decrease obviously, with laser energy equivalence linear energy transfer (ELET) decrease much more. All the results mentioned above show that DD will distinctly affect SEB capabilities of SiC chips, DD will induce a leakage current path, which will decrease SEB threshold LET when SEE will also cause a leakage current path.

3-D Stacking of SiC Integrated Circuit Chips With Gold Wire Bonded Interconnects for Long-Duration High-Temperature Applications

Silicon carbide integrated circuits (SiC ICs) have been demonstrated to operate at high temperatures, such as ~460 °C at the Venus’ surface, for two months, and for over a year at 500 °C. At these high temperatures, the SiC integrated circuits and sensors need to be packaged in quite different ways than those below 300 °C. In addition, to integrate more devices into the limited footprint of the high-temperature circuit board, three-dimensional (3-D) packaging is a notable advantage. In this work, 3-D stacking of SiC chips using a gold wirebonding interconnect is investigated. The gold bonding wire is used due to its mechanical robustness and chemical inertness at high temperatures. Triple-stacked SiC chips are bonded to each other and to the gold conduction pads on the alumina substrate with screen-printed gold pastes. The mechanical die shear test, wire pull tests, and interconnect electrical resistance tests are executed and analyzed before and after the 3-D SiC chip packages are subject to a 600 °C thermal aging process in the air for up to 10 days. This 3-D SiC chip packaging has promise for long-duration high-temperatures (up to 600 °C) applications and may be potential for use for applications such as Venus’s surface sensing and telemetry.

Effects of substrate bias on the sputtering of high density (111)-nanotwinned Cu films on SiC chips

This article presents a study of the influence of the substrate bias on the microstructure, preferred orientation, and mechanical and electrical properties of nanotwinned Cu film. The formation of a nanotwinned structure and (111) surface orientation can be properly controlled by applied substrate bias. High density nanotwinned structures were introduced into Cu films sputtered on SiC substrates with over 90% of (111)-orientation at − 150 V. Densely packed Cu nanotwins were observed within the columnar grains stacked up on each other along the film growth direction, with an average twin spacing of 19.4 nm. The Cu films deposited on SiC substrate via bias sputtering had surface roughness of 8.6 to 15.8 nm. The resistivity of the copper nanotwinned films sputtered with various substrate biases varied. The optimal indentation, 2.3 GPa, was found in the nanotwinned Cu film sputtered with a bias voltage of − 150 V. The effects of Ar ion bombardment on microstructure, surface morphology and properties are further discussed.

Bonding strength enhancement of low temperature sintered SiC power module by femtosecond laser induced micro/nanostructures

In this work, a low-temperature and low-pressure method was proposed for the bonding strength enhancement of SiC chips and substrates using micro/nanostructures fabricated by femtosecond laser. It is demonstrated that a reliable bond was achieved at 180 °C without assistant pressure. When the sintering temperature reached 250 °C and the assistant pressure was 10 MPa, the average shear strength reached 45 MPa, which was more than 3 times that of the flat substrate. The fracture surface morphology and the cross-section of the sample were characterized by SEM to analyze the enhancement mechanism of shear strength. The shear strength under different sintering conditions was also discussed. The thermomechanical coupled finite element simulation results demonstrate that the power module possessed excellent thermal capability and reliable lifetime under a temperature shock environment (−50 °C–250 °C). It is proved that the measured temperature distribution of the joint is in agreement with the simulation results. This method has great application prospects in microelectronic packaging, especially for wide-bandgap power semiconductors.

Robust shear strength of Cu–Au joint on Au surface-finished Cu disks by solid-state nanoporous Cu bonding

The metallization process has received significant attention in the electronic industry. It is one of the best method to enhance bonding strength via interfacial reaction between the back side metallization layer of the SiC chip and an insert material while facilitating superior electrical and thermal conductivity along with excellent chemical resistance. This study is aimed at understanding the effect of the bonding temperatures (200–400°C) on the shear strength of the joints formed between the nanoporous Cu (NPC) sheets and Ni(P)/Au surface-finished Cu disks for the replacement of the high-Pb-containing solder joint in high-temperature applications (> 300°C). We observed that the mechanical properties depend not only on the porosity of the NPC layer but also on the interfacial reaction between the NPC and Au layer of NPC bonding joints. The shear test confirmed the shear strength of the NPC bonding joints above 300°C to be 28 MPa, which was higher than that of conventional high-Pb-containing solder and sintered Cu nanoparticle joints. To understand this promising result, the bonding microstructure was investigated via scanning electron microscopy (SEM), electron probe micro-analyzer (EPMA), and transmission electron microscopy (TEM) analyses. The present study revealed that the shear strength of NPC bonding is closely related to the microstructural characteristics, which are driven by the densification reaction of the NPC layer through the surface diffusion of Cu atoms and interdiffusion reaction between the NPC and Au layer according to the bonding temperature. Based on these results, a mechanism was proposed to explain the superiority of the NPC bonding joints on Ni(P)/Au surface-finished Cu disks achieved using this method.

Pressureless Sintered-Silver as Die Attachment for bonding Si and SiC Chips on Silver, Gold, Copper, and Nickel Metallization for Power Electronics Packaging: The Practice and Science

Low-temperature silver (Ag) sintering is emerging as a cutting-edge die-attach technology for power electronics packaging. However, the industry still has concerns about completely accepting this technology. One of the reasons is a lack of knowledge about the mechanism and process of sintered silver bonding on various metallization. Before, we reported a preliminary assessment of the die-shear strength and microstructures of Si dummy device attached on Ag, Au, and Cu metallization. This research will go deeper into the practice and science of attaching Si and SiC devices with sintered-Ag on substrates with up to seven most widely used metallizations, including electroplated Ag, Ni/Au, and Ni, electroless-plated Ni(P)/Ag, Ni(P)/Au, and Ni(P), and native Cu on DBC substrate. All sintered-Ag die-attach were pressureless in the air at temperatures ranging from 220 °C to 300 °C. The mechanical, electrical, and thermal parameters, as well as the microstructural analyses, were assessed. The purpose of this research is to gain a better understanding by: 1) discussing effects of devices and substrate metallizations on the mechanical, electrical, and thermal characteristics; 2) reviewing fundamental mechanisms of interfacial adhesion for sintered-Ag bonding, and 3) providing practical considerations for developing Si and SiC sintered-Ag die-attaching profiles on the widely used substrate metallization.

Online Junction Temperature and Current Simultaneous Extraction for SiC MOSFETs With Electroluminescence Effect

In this letter, a junction-temperature and current extraction method is presented based on the electroluminescence mechanism of the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> body diode. Starting from the observation of two characteristic peaks in the emitted light spectrum, we proved that the junction temperature and the drain current can be simultaneously measured. This novel method consists of decoupling the relationship between the intensity of the electroluminescence peaks, the current, and the temperature. Through this optical method with inherent electrical isolation, the junction temperature and current in the SiC chip can be simultaneously measured with high precision. The total error of the junction temperature estimation is within ±3 °C, and the error of the current estimation is about ±0.2 A.

Study of Thermal Stress Fluctuations at the Die-Attach Solder Interface Using the Finite Element Method

Solder joints in electronic packages are frequently exposed to thermal cycling in both real-life applications and accelerated thermal cycling tests. Cyclic temperature leads the solder joints to be subjected to cyclic mechanical loading and often accelerates the cracking failure of the solder joints. The cause of stress generated in thermal cycling is usually attributed to the coefficients of thermal expansion (CTE) mismatch of the assembly materials. In a die-attach structure consisting of multiple layers of materials, the effect of their CTE mismatch on the thermal stress at a critical location can be very complex. In this study, we investigated the influence of different materials in a die-attach structure on the stress at the chip–solder interface with the finite element method. The die-attach structure included a SiC chip, a SAC solder layer and a DBC substrate. Three models covering different modeling scopes (i.e., model I, chip–solder layer; model II, chip–solder layer and copper layer; and model III, chip–solder layer and DBC substrate) were developed. The 25–150 °C cyclic temperature loading was applied to the die-attach structure, and the change of stress at the chip–solder interface was calculated. The results of model I showed that the chip–solder CTE mismatch, as the only stress source, led to a periodic and monotonic stress change in the temperature cycling. Compared to the stress curve of model I, an extra stress recovery peak appeared in both model II and model III during the ramp-up of temperature. It was demonstrated that the CTE mismatch between the solder and copper layer (or DBC substrate) not only affected the maximum stress at the chip–solder interface, but also caused the stress recovery peak. Thus, the combined effect of assembly materials in the die-attach structure should be considered when exploring the joint thermal stresses.

Modeling and Analysis of Silver-Sintered Molybdenum Packaging for SiC Power Modules With Improved Lifetime and Temperature Range

With the application of wide bandgap devices, the packaging technology of power modules is faced with elevated challenges. This paper proposes a new packaging concept for silicon carbide power modules. The main objective is to improve the lifetime and temperature range, while the proposed packaging also has the potential to reduce stray inductance and simplify the fabrication process. In the proposed concept, sintered nano-silver is selected as the die bonding. The conventional direct-bonded-copper substrate is replaced by a molybdenum layer and a bismaleimide triazine resin layer which has a low thermal expansion coefficient. A steady-state thermal-mechanical analysis is conducted to verify the material selection. Furthermore, a transient thermal-mechanical analysis based on JEDEC temperature cycling methods is carried out, whose results are applied in the Coffin-Manson lifetime model to evaluate the advantages of the proposed Silver-Sintered Molybdenum Packaging. The results demonstrated that the proposed packaging technology could improve the lifetime by over 1000 times and increase the maximum operating temperature by nearly 3 times. Finally, a feasible process of sintering SiC chips on molybdenum substrates is proposed, which achieves a uniform and low porosity bonding.

Sintering of SiC chip via Au80Sn20 solder and its joint strength and thermomechanical reliability

The metallic packaging remains a big challenge for solid-state, high-power-density electronic devices, such as SiC chips, due to the frequent failure of solder joints in these components. Herein, the SiC Schottky diode was successfully soldered on a Mo substrate using eutectic Au80Sn20 solder at a low temperature of 320 °C. The results show excellent reliability and performance of the SiC chips. The chips can maintain outstanding performance after 2000 h at 280 °C and 500 cycles of heating and cooling experiments. Hence, this study demonstrates that this welding method has potential applications in high-power SiC chips with excellent thermomechanical reliability.

Fatigue crack evolution and effect analysis of Ag sintering die-attachment in SiC power devices under power cycling based on phase-field simulation

Sintering Ag materials is a promising candidate for the die-attachments in SiC power devices due to its high melting point and low thermal resistance. However, CTE mismatch between the SiC chips and the substrates causes cracks to develop in the sintered interconnection structures. Power cycling conditions lead to periodic loadings on the Ag sintering die-attachment. The incremental accumulation of plastic strain energy, combined with periodic fluctuations of elastic strain energy, results in the fatigue crack evolutions of the sintered structures. Further, the crack evolutions considerably degrade the thermal and mechanical properties of the interconnect structure, and critically affects the integrity of the heat transfer network and the mechanical structure of the power devices. In this paper, the fatigue crack evolution of Ag sintering die-attachment in the SiC power devices is simulated based on the phase-field models. Moreover, the thermal performance degradations and stress distributions of die-attachment under power cycling are analysed. A methodology based on finite element modelling and phase-field simulation is proposed, realised by Abaqus and its subroutines. The fatigue crack in the Ag sintering die-attachment initiates from the chip-side corner point, then propagates to the chip-side centre point until the formation of a penetrative crack, which achieves a good match with experimental results. Moreover, along with the crack propagation, the thermal distributions in the chip and the stress distributions of the sintering layer are obtained to analyse the degradations of thermal and mechanical performances of Ag sintering die-attachment in SiC power devices.

A Way to Reduce Leakage Current and Improve Reliability of Wire-Bonds for 300-A Multichip SiC Hybrid Modules

In this article, pressureless sintering of nanosilver paste is proposed to enhance the reliability of wire-bonds with SiC chips by both alleviating thermomechanical stresses and enhancing thermal coupling of bonding wires and chips. A multichip 1200-V/300-A SiC hybrid module with six Si IGBTs and 12 SiC Schottky barrier diodes (SBDs) is demonstrated. The lifetime of the wire-bonds with the SiC SBD bonded by the pressureless sintered nanosilver is ~27.9% longer than that by the high-temperature solder under power cycling with constant temperature swing. The lifetime of the wire-bonds with the IGBT also bonded by the pressureless sintered nanosilver is ~46.2% longer than that by the high-temperature solder under power cycling with constant conduction current. Furthermore, not only the cost of 1700-V SiC SBDs is quite similar to that of 1200-V ones but also the leakage current of the 1200-V/300-A SiC hybrid module can be reduced greatly using 1700-V SiC SBDs as free-wheeling diodes instead of the regular 1200-V ones. Considering the much larger leakage current of a SiC SBD compared with that of a Si p-i-n diode. It is feasible to use a SiC SBD with higher blocking voltage to reduce the significant leakage current of the free-wheeling SBD with almost no cost increase.