Abstract
Solder joints in electronic packages are frequently exposed to thermal cycling in both real-life applications and accelerated thermal cycling tests. Cyclic temperature leads the solder joints to be subjected to cyclic mechanical loading and often accelerates the cracking failure of the solder joints. The cause of stress generated in thermal cycling is usually attributed to the coefficients of thermal expansion (CTE) mismatch of the assembly materials. In a die-attach structure consisting of multiple layers of materials, the effect of their CTE mismatch on the thermal stress at a critical location can be very complex. In this study, we investigated the influence of different materials in a die-attach structure on the stress at the chip–solder interface with the finite element method. The die-attach structure included a SiC chip, a SAC solder layer and a DBC substrate. Three models covering different modeling scopes (i.e., model I, chip–solder layer; model II, chip–solder layer and copper layer; and model III, chip–solder layer and DBC substrate) were developed. The 25–150 °C cyclic temperature loading was applied to the die-attach structure, and the change of stress at the chip–solder interface was calculated. The results of model I showed that the chip–solder CTE mismatch, as the only stress source, led to a periodic and monotonic stress change in the temperature cycling. Compared to the stress curve of model I, an extra stress recovery peak appeared in both model II and model III during the ramp-up of temperature. It was demonstrated that the CTE mismatch between the solder and copper layer (or DBC substrate) not only affected the maximum stress at the chip–solder interface, but also caused the stress recovery peak. Thus, the combined effect of assembly materials in the die-attach structure should be considered when exploring the joint thermal stresses.
Highlights
With the development of semiconductor technologies, SiC, GaN and other thirdgeneration semiconductor materials with wide band-gap characteristics are widely used in power modules [1]
The stress recovery peak should be attributed to the superposition of two stresses generated by the chip–solder layer coefficients of thermal expansion (CTE) mismatch and the solder layer and copper layer CTE mismatch
The finite element method was used to analyze the effects of boundary conditions and modeling scopes on the stress at the chip–solder layer interface during thermal cycling
Summary
With the development of semiconductor technologies, SiC, GaN and other thirdgeneration semiconductor materials with wide band-gap characteristics are widely used in power modules [1]. The SiC chip is generally attached to the circuit board through a solder layer (i.e., die-attach structure), which provides mechanical support and heat dissipation protection for the chip [2,3]. In order to meet the requirements of die-attach technologies and the Restriction of Hazardous Substances (RoHS) directive, a series of die-attach materials, such as Sn– Ag, Sn–Ag–Cu (i.e., SAC) solder alloys and sintering silver paste were developed [7,8,9]. Among them, cracking failures caused by temperature fatigue account for about 55% of die-attach structure failure [12]. Clarifying the causes of cracking during temperature cycling is of great value to power module reliability
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