Si Tunnel Field Effect Transistor Research Articles

A new line tunneling SiGe/Si iTFET with control gate for leakage suppression and subthreshold swing improvement

This article presents a new line tunneling dominating metal–semiconductor contact-induced SiGe–Si tunnel field-effect transistor with control gate (CG-Line SiGe/Si iTFET). With a structure where two symmetrical control gates at the drain region are given a sufficient negative bias, the overlap of the energy bands at the drain in the OFF-state is effectively suppressed, thus reducing the tunneling probability and significantly decreasing leakage current. Additionally, the large overlap area between the source and gate improves the gate’s ability to control the tunneling interface effectively, improving the ON-state current and subthreshold swing characteristics. By using the Schottky contact characteristics of a metal–semiconductor contact with different work functions to form a PN junction, the need to control doping profiles or random doping fluctuations is avoided. Furthermore, as ion implantation is not required, issues related to subsequent annealing are also eliminated, greatly reducing thermal budget. Due to the different material bandgap characteristics selected for the source and drain regions, the probability of overlap of the energy bands in the source region in the ON-state is increased and that in the drain region in the OFF-state is reduced. Based on the feasibility of the actual fabrication process and through rigorous 2D simulation studies, improvements in subthreshold swing and high on/off current ratio can be achieved simultaneously based on the proposed device structure. Additionally, the presence of the control gate structure effectively suppresses leakage current, further enhancing its potential for low-power-consumption applications.

Performance Boost of Si TFETs by Insertion of III–V Dipole Formation Layer: A First Principle Study

Silicon channel tunnel field-effect transistors (TFETs) are known to exhibit low ON-state current due to the wide indirect band gap. In this work, to achieve high ON-state current, we propose a Si TFET with an ultra-thin dipole formation layer (DFL) inserted at the source/channel junction. The inserted DFL forms charge transfer dipoles at the interface, resulting in a staggered band gap. As the consequence, the effective tunnel barrier for electrons is significantly lowered so that ON-state current increases by orders of magnitude. To analyze the characteristics of DFL-inserted Si TFETs, we have solved nonequilibrium Green’s function (NEGF) and Poisson’s equation using density functional theory (DFT) Hamiltonians. We demonstrate that DFL-inserted Si TFETs show boosted performance over conventional TFETs, exhibiting high ON-state current and steep subthreshold swing (SS).

SiGe vertical NW GAA TFET with improved current and low leakage

A comparative study of the double gate MOSFET (DG MOSFET), vertical silicon gate all around nanowire (GAA-NW) tunneling field effect transistor (TFET) and SiGe-source HfO2-insulator GAA-NW TFET is presented to prove that the last can outperform the others in terms of high performance, energy efficiency, ultra-low power, high on-chip density and gate controllability. Scaling of transistors beyond FinFET is generally possible with the help of TFET while reducing the subthreshold swing (SS), short channel effects (SCE) and drain induced barrier leakage (DIBL). But the ambipolarity in Si TFET causes high Ioff current. Hence, here, a vertical Si-source SiO2-insulator GAA-NW TFET is studied to provide high Ion current, subthreshold swing less than 30 mV/decade and DIBL less than 20 mV/V, so that the channel length can be made independent of the footprint. These properties are further enhanced by the use of SiGe source and HfO2 insulator.

Si bilayer tunnel field-effect transistor structure realized using tilted ion-implantation technique

A new device structure for the Si tunnel field-effect transistor (TFET) is proposed along with feasible fabrication processes. The device consists of a Si fin with high impurity concentration at the fin surfaces, which are realized using the tilted-ion-implantation technique (TII) to effectively generate the gate-normal band-to-band tunneling (BTBT) and simultaneously create carrier conduction paths from the source to the drain. Device simulation revealed that the asymmetric impurity distribution, with a higher concentration on the source side and a lower concentration on the drain side controlled by the TII energy and angle, has potential for the realization of a high eGR/hGR by reducing the BTBT distance and a low off-state leakage. As a result, a steep on/off switching with a current ratio greater than 105 under an operating voltage of 0.3 V can be achieved by careful optimization of the implanted impurity distributions.

Operational transconductance amplifier designed with nanowire tunnel-FET with Si, SiGe and Ge sources using experimental data

In this paper operational transconductance amplifiers (OTA) were designed with nanowire (NW) tunnel field effect transistors (TFET) with different source materials (Si, SiGe, and Ge) and compared with NW Si MOSFET devices. Lookup tables with experimental data were used to model the transistors and simulate the OTAs. At the same dimensions and transistor efficiency region, the TFET OTAs have larger gain than the MOSFET circuit. The Ge-source TFET OTA presents the highest differential gain (105 dB), followed by the Si TFET (96 dB) and the SiGe-source TFET (90 dB), with the MOSFET presenting the lowest gain (51 dB). However, the MOSFET has the best gain-bandwidth product (GBW) (9.2 MHz) followed by the Ge-source TFET (1.6 MHz), the SiGe-source TFET (900 kHz) and the Si TFET (41 kHz). The second group of OTAs, where the same power consumption was considered and where the gain of the MOSFET OTA and the GBW of the TFETs’ circuits were increased was also studied. The gain of the MOSFET OTA increased to 56 dB, but it is still lower than the TFET circuits (96, 90 and 102 dB for the Si TFET, SiGe-source TFET and Ge-source TFET, respectively). The GBW of the Si TFET, SiGe-source TFET and Ge-source TFET circuits increased to 71 kHz, 1 MHz, and 2 MHz, respectively. Nevertheless, the MOSFET OTA has the best GBW (4.7 MHz) again but being just 2.35 times the GBW of the Ge-source TFET case. Therefore, because of the high gain of the TFETs OTAs, they are indicated for low power, low-frequency applications, with the Ge-source TFET presenting a good compromise between gain and GBW. The circuits’ linearity was also verified, and they demonstrate to be more dependent on bias choices than on the devices themselves.

Surface Ge-rich p-type SiGe channel tunnel field-effect transistor fabricated by local condensation technique

In this study, tunnel field-effect transistor (TFET) which has surface Ge-rich SiGe nanowire as a channel has been demonstrated. There are improvements in terms of on-current and subthreshold swing (SS) comparing with control groups (constant Ge concentration SiGe TFET and Si TFET) fabricated by the same process flow except for the channel formation step. In order to obtain the concentration-graded SiGe channel, Ge condensation method which is a kind of oxidation is adopted. The rectangular shape of the channel becomes a rounded nanowire through the Ge condensation process. The TFET with the concentration-graded SiGe channel can improve drive current due to a smaller band gap at the Ge-condensed surface of the channel compared to Si or non-condensed SiGe channel TFET.

Analysis of Miller Capacitance in Si Tunnel Field-Effect Transistors and Potential for Low-Voltage/Low-Energy Applications

The purpose of this paper is to analyze the reason why the gate-to-drain capacitance (Miller capacitance) of a tunnel FET (TFET) is very large, and to reveal key aspects of the capacitance components of TFET. A numerical device simulator is used to compare lateral and vertical TFET performance. It is demonstrated that the Miller capacitance of the devices, particularly the lateral TFET, can be drastically reduced without degrading the drivability, by using gate-to-drain off-set. It is also demonstrated that while vertical TFETs are promising for decreasing the switching delay, they suffer the fatal demerit of poor drivability when scaled. In addition, this paper tackles the numerical modelling of TFET capacitance components in order to appropriately estimate switching delay time of the devices; no reliable model has been proposed for TFETs to date. It is shown that the capacitance model leads to better estimates of switching delay times of TFETs than the conventional estimation method.

Influence of Doping and Splitting of Source in a Group IV Material Based Tunnel Field Effect Transistor

In this work, the effect of abrupt source doping in a tunnel field effect transistor (TFET) using SiGe as the source and drain material is investigated for future low-voltage and high-power applications. The effect of critical device factors, such as dielectric material and gate oxide thickness and dependency on the mole fraction, are examined. The results of the proposed SiGe-Si-SiGe TFET structure are compared with existing data of Si TFET and SiGe-Si-Si TFET with and without abrupt doping. The proposed structure shows better ION/IOFF ratio of the order of 1011 and a sub-threshold swing of 18.18 mV/decade, which ensures fast switching applications of the device.

Simulation of planar single-gate Si tunnel FET with average subthreshold swing of less than 60 mV/decade for 0.3 V operation

Planar single-gate (SG) silicon (Si) tunnel field effect transistors (TFETs) are attracting interest for ultra-low voltage operation and CMOS applications. For the achievement of subthreshold swing (S.S.) less than thermal limit of Si MOSFETs (S.S. = 60 mV/decade at 300 K), previous studies have proposed the formation of a pocket region, which needs very difficult implantation process. In this work, a planar SG Si TFET without pocket was proposed by using the technology computer-aided design (TCAD) simulations. An average S.S. of less than 60 mV/decade for 0.3 V (= Vgs = Vds) operation was obtained. It is found that both low average S.S. (= 27.8 mV/decade) and high on-current Ion (= 3.8 µA/µm) are achieved without pocket doping by scaling the equivalent oxide thickness (EOT) and increasing the gate-to-source overlap length Lov.

The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of In<italic>x</italic>Ga1–<italic>x</italic>As nTFETs

The basic analog parameters of three splits of In x Ga1– x As nTFETs are analyzed for the first time. The first two splits are In0.53Ga0.47As devices with a 3-nm HfO2/1-nm Al2O3 and a 2-nm HfO2/1-nm Al2O3, while the last one is an In0.7Ga0.3As channel with a 3-nm HfO2/1-nm Al2O3 gate. The low equivalent oxide thickness improves the electrostatic coupling, enhancing ${I}_{{\text {DS}}}$ , and, consequently, also gm and ${A}_{V}$ , especially for higher $\text {V}_{{\text {GS}}}$ . The InGaAs tunnel field-effect transistors (TFETs) show compatible performance with Si TFETs, and have better performance than Si MOSFETs, making them useful for low-power and low-voltage analog applications. The highest efficiency is found using the combination of a 2-nm HfO2 with In0.53Ga0.47As, due to the 56-mV/dec subthreshold swing obtained. For all splits, the ${A}_{V}$ peak can be related to the ${V}_{{\text {GS}}}$ necessary for band-to-band tunneling to become the dominant transport mechanism.

Investigation of ft and fmax in Si and Si1–xGex based single and dual material double-gate Tunnel FETs for RF applications

This study optimizes Si1−xGex based double gate tunnel field effect transistor (TFET) for their high ON current (Ion) and lesser sub-threshold swing and compares Si and Si1−xGex based single material double gate (SMDG) and dual material double gate (DMDG) TFETs. This study also measures the two RF performance metrics, unity gain cut-off frequency (ft) and maximum oscillation frequency (fmax) by varying the structural parameters, gate length, gate oxide thickness, channel thickness and underlap. Compared to single material gate devices, dual material gate devices give higher Ion without compromising the leakage current for both Si and Si1−xGex based TFETs. Si1−xGex based TFETs offers higher ft and fmax compared to that of Si TFETs for all the structural parameter variations considered in this study. DMDG TFETs exhibit higher ft with respect to SMDG TFETs. SMDG TFETs offers more fmax compared to DMDG TFETs due to the smaller values of output conductance.

A Si tunnel field-effect transistor model with a high switching current ratio and steep sub-threshold swing

A novel double-gate tunneling field effect transistor (PNIN-P TFET) device structure, in which two pockets were inserted near the source side at the source-channel junction and placed in the middle of the additional underlap region between the channel and drain, respectively, is proposed to improve the performance of the tunneling field effect transistor (TFET). The device was found to possess the advantages of the source-pocket TFET (PNIN TFET) and the tunnel-induced injection field-effect transistor (TI-FET) simultaneously. A steep subthreshold swing (∼35 mV dec−1) and an excellent switching state current ratio (∼1012) were obtained at room temperature, indicating that this device is a promising candidate as a replacement for the traditional MOSFETs.

Tunneling field-effect transistor with Si/SiGe material for high current drivability

In order to overcome the small current drivability of a tunneling field-effect transistor (TFET), we have introduced a TFET with the SiGe body and elevated Si drain region. The proposed TFET features large on-current and lower subthreshold swing (SS) compared with the Si TFET. Also, by using elevated Si drain region, it is expected that ambipolar current can be suppressed. Through the technology computer aided design (TCAD) simulation, the characteristics of the proposed TFET have been investigated to confirm its superiority in performance. The proposed TFET structure enables self-aligned doping process and has a strong immunity to short-channel effects compared with the conventional TFET. In addition, we have confirmed that both n- and p-channel characteristics can be simultaneously improved by using the proposed TFET.

A Silicon Tunnel Field-Effect Transistor with an In Situ Doped Single Crystalline Ge Source for Achieving Sub-60 mV/decade Subthreshold Swing

We report the demonstration of an n-channel lateral Si tunnel field-effect transistor (TFET) with a single crystalline Ge source fabricated using the gate-last process. The p+ Ge source was in situ doped and grown at 320°C. An abrupt interface between Ge source and Si channel with type-II band alignment and a steep source doping profile (∼1.5 nm/decade) formed the tunneling junction. This allows the realization of a TFET with a steep subthreshold swing of 49 mV/decade at room temperature and an ION/IOFF ratio of 107.

Tunnel Field-Effect Transistor with Epitaxially Grown Tunnel Junction Fabricated by Source/Drain-First and Tunnel-Junction-Last Processes

We fabricate p- and n-channel Si tunnel field-effect transistors (TFETs) with an epitaxially grown tunnel junction. In a novel source/drain-first and tunnel-junction-last fabrication process, a thin epitaxial undoped Si channel (epichannel) is deposited on a preferentially fabricated p- or n-type source area. The epichannel sandwiched by a gate insulator and a highly doped source well acts as a parallel-plate tunnel capacitor, which effectively multiplies drain current with an enlarged tunnel area. On the basis of its simple structure and easy fabrication, symmetric n- and p-transistor and complementary metal oxide semiconductor inverter operations were successfully demonstrated.

Improved Subthreshold and Output Characteristics of Source-Pocket Si Tunnel FET by the Application of Laser Annealing

To reduce the power consumption and improve the device performance in scaled CMOS integrated circuits, transistors with steep subthreshold swing (SS) is highly desirable. The tunnel field-effect transistor (TFET) based on the band-to-band tunneling has been suggested as a replacement to conventional MOSFETs. In order to improve the device performance of TFET, enhanced carrier transport across the tunneling junction is crucial. In this paper, source-pocket Si TFET is presented and successfully fabricated by laser annealing. This TFET has enhanced lateral electric field across the source tunneling junction, resulting in a reduction of tunneling distance. The experimental data of the proposed paper, for the first time, shows steep SS (46 mV/dec at 1 pA/μm), excellent ION/IOFF ratio ( <; 107), and improved output characteristics at T = 300 K due to the dramatic reduction of the tunneling resistance. Compared with other TFET works, the proposed method is efficient to improve the device performance on TFET.

Lateral energy band profile modulation in tunnel field effect transistors based on gate structure engineering

Choosing novel materials and structures is important for enhancing the on-state current in tunnel field-effect transistors (TFETs). In this paper, we reveal that the on-state performance of TFETs is mainly determined by the energy band profile of the channel. According to this interpretation, we present a new concept of energy band profile modulation (BPM) achieved with gate structure engineering. It is believed that this approach can be used to suppress the ambipolar effect. Based on this method, a Si TFET device with a symmetrical tri-material-gate (TMG) structure is proposed. Two-dimensional numerical simulations demonstrated that the special band profile in this device can boost on-state performance, and it also suppresses the off-state current induced by the ambipolar effect. These unique advantages are maintained over a wide range of gate lengths and supply voltages. The BPM concept can serve as a guideline for improving the performance of nanoscale TFET devices.

An Improved Si Tunnel Field Effect Transistor With a Buried Strained $\hbox{Si}_{1-x}\hbox{Ge}_{x}$ Source

We report on experimental and simulated results of tunneling field-effect transistors (TFETs) with a Si channel and a strained Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> source. The fabricated TFET with a tensile strained Si channel shows comparably large on-currents and a subthreshold slope of 80 mV/dec at 300 K for a drain current range of three orders of magnitude. A novel TFET structure is proposed to enhance the on-currents by using a buried Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> source. The overlap between the top thin Si channel and the buried SiGe source increases the tunneling area. Simulations indicate that this structure significantly improves the performance.

On Enhanced Miller Capacitance Effect in Interband Tunnel Transistors

We compare the transient response of double-gate thin-body-silicon interband tunnel field-effect transistor (TFET) with its metal-oxide-semiconductor field-effect transistor counterpart. Due to the presence of source side tunneling barrier, the silicon TFETs exhibit enhanced Miller capacitance, resulting in large voltage overshoot/undershoot in its large-signal switching characteristics. This adversely impacts the performance of Si TFETs for digital logic applications. It is shown that TFETs based on lower bandgap and lower density of states materials like indium arsenide show significant improvement in switching behavior due to its lower capacitance and higher ON current at reduced voltages.