Si Submount Research Articles

3D Integrated Laser Attach Technology on a 300-mm Monolithic CMOS Silicon Photonics Platform

Enabling cost-effective and power-efficient laser source on a silicon photonics (SiPh) platform is a major goal that has been highly sought after. In the past two decades, tremendous effort has been made to develop various on-chip integration techniques to enhance SiPh circuits with efficient light-emitting materials. Here we review our recent advancements in hybrid flip-chip integration of III-V lasers on a 300-mm monolithic SiPh platform. By leveraging advanced complementary metal oxide semiconductor (CMOS) manufacturing processes, we have demonstrated wafer-scale laser attach based on a precisely controlled cavity formed on a silicon-on-insulator (SOI) substrate. The laser integration process is aided by precise mechanical alignment features on the SiPh wafer and high-precision fiducials on the laser. Efficient laser-to-SiPh-circuit butt-coupling with optical power up to 20mW was demonstrated through wafer- and module-level characterizations. Key performance metrics including side-mode suppression ratio, mode-hopping, and relative intensity noise were characterized after laser integration. In addition, early reliability assessments were performed on laser-attached SOI wafers and Si submount assemblies to understand the long-term performance stability of the lasers on the monolithic platform. To further enhance the performance of the laser-integrated chip, we explored alternative spot-size converters that could simultaneously enable improved coupling efficiency and relaxed fabrication tolerance, thus showing great promise over traditional designs.

Research on dynamic thermal performance of high-power ThinGaN vertical light-emitting diodes with different submounts

Investigation of dynamic thermal performance is a key to improve the heat management of high-power (HP) vertical light-emitting diodes (VLEDs). Specifically, the thermal time constant is a crucial parameter for optimizing the design and reliability of HP LEDs. Herein, the dynamic thermal behavior of seven HP ThinGaN VLEDs with different constructions was demonstrated. The LEDs’ thermal parameters were measured through the thermal transient tester system by a forward voltage technique. A three-stage of multiexponential function model was applied to divide the transient response curve into three regions with different thermal properties. This study focused on analyzing the first region that involved the chip region (epitaxial layer, wafer bonding layer, and submount) and chip bonding layer. The submounts of the LEDs under consideration include silicon carbide (SiC), silicon (Si), sapphire (Al2O3), and germanium (Ge). The results revealed that with a qualified wafer bonding layer, the LED packages with SiC, Si, and Al2O3 submount presented the optimum thermal time constant, which was 85, 69, 75, and 81 ms, respectively.

Investigation of Wafer Level Packaging schemes for 3D RF interposer multi-chip module

Abstract Very small RF modules can be realized through heterogenous integration of GaAs MMIC (monolithic microwave integrated circuit) onto a low loss Si sub-mount, with high density routing lines realized by advanced patterning. In this paper we investigate how to integrate MMIC active devices on GaAs with the RF passives produced on an interposer, using Si wafer process technology. High resistive Silicon substrates are required to minimize RF losses. The interposer is thinned below 100 μm to reveal Cu TSVs from the back of the interposer, while the front side is covered entirely with a silicon capping wafer for shielding the device. We compare different wafer level packaging approaches for producing the low RF-loss interposers, and populating them using die-to-die (D2D) or die-to-wafer (D2W) bonding of the MMIC components, followed by wafer level encapsulation. Two D2W approaches are compared, in the first approach the D2W mounting and the encapsulation happens before the Si interposer is thinned for TSV reveal. To avoid damage during thinning of the wafer, thicker substrates with deeper TSV of 150 μm or more are required. In a second approach, the thinning of the interposer is done prior to the mounting. Initial electrical data showed that the approach yielded proper RF performance, but further yield optimization is required.

실리콘 서브 마운틴 기반의 LED 패키지 재료평가 및 신뢰성 시험

The light emitting diodes(LED) package of new structure is proposed to promote the reliability and lifespan by maximize heat dissipation occurred on the chip. We designed and fabricated the LED packages mixing the advantages of chip on board(COB) based on conventional metal printed circuit board(PCB) and the merits of Si sub-mount using base as a substrate. The proposed LED package samples were selected for the superior efficiency of the material through the sealant properties, chip characteristics, and phosphor properties evaluations. Reliability test was conducted the thermal shock test and flux rate according to the usage time at room temperature, high-temperature operation, high-temperature operation, high-temperature storage, low-temperature storage, high-temperature and high-humidity storage. Reliability test result, the average flux rate was maintained at 97.04% for each items. Thus, the Si sub-mount based LED package is expected to be applicable to high power down-light type LED light sources.

Effect of wafer bonding and laser liftoff process on residual stress of GaN-based vertical light emitting diode chips

Residual stress conditions in GaN-based LEDs will have a significant influence on device performance and reliability. In this paper, GaN-based vertical LEDs under different stress conditions are fabricated by bonding with three types of submounts (Al2O3 submount, CuW submount and Si submount), changing the soak temperature (290 ℃, 320 ℃, 350 ℃ and 380 ℃) and using different laser energy densities (875, 945 and 1015 mJ·cm-2). The warpage and Raman scattering spectra of those GaN-based LEDs are measured. The experimental results show that the residual stress conditions in GaN-based vertical LEDs are a consequence of the bonded submounts and bonded metal, and the soak temperature is the primary factor that determines the degree of residual stress in LED chips. In the laser lift-off process, changing laser energy density in an appropriate range has little influence on residual strain of LED chips, and the micro-cracks in GaN layer caused by LLO process will play a role in releasing the residual stress. The warpage of epitaxial sapphire substrate becomes large after boding with Si submount, the residual stress in GaN-based vertical LEDs is tensile stress and becomes larger with the soak temperature rising. When GaN epi wafer bonds with Al2O3 submount and CuW submount, the warpages becomes small and large respectively and the residual stress in chips is compressive stress. Because of the mismatch of coefficient of thermal expansion, the compressive stress in GaN-based LED chips increases for Al2O3 submount and drops for CuW submount with the soak temperature rising.

The Effects of Si Submounts Containing Cu Thermal Vias on the Heat-Dissipation Characteristics of a High-Power Light-Emitting Diode Package

We investigated the effects of Si submounts containing Cu thermal vias on the heat-dissipation characteristics of a high-power light-emitting diode (LED) package. Simulations were used to determine the optimum conditions for effective heat dissipation from the LED. The optimum thickness of the Si submount containing the Cu thermal vias was 250 μm. The optimum heat flux area ratio between the Si submount and the LED chip was 25. The thermal resistance of an Si submount 250 μm thick and 25 mm2 in area was 1.85 K/W without Cu vias. This value decreased to 1.50 K/W on incorporation of the 400-μm-diameter Cu vias. In addition, the total thermal resistance of the LED package structure was improved from 9.7 K/W to 8.3 K/W on incorporation of the 400-μm-diameter Cu vias into the Si submount.

Thermal simulation and analysis of flat surface flip-chip high power light-emitting diodes

Conventional GaN-based flip-chip light-emitting diodes (CFC-LEDs) use Au bumps to contact the LED chip and Si submount, however the contact area is constrained by the number of Au bumps, limiting the heat dissipation performance. This paper presents a flat surface high power GaN-based flip-chip light emitting diode (SFC-LED), which can greatly improve the heat dissipation performance of the device. In order to understand the thermal performance of the SFC-LED thoroughly, a 3-D finite element model (FEM) is developed, and ANSYS is used to simulate the thermal performance. The temperature distributions of the SFC-LED and the CFC-LED are shown in this article, and the junction temperature simulation values of the SFC-LED and the CFC-LED are 112.80 °C and 122.97 °C, respectively. Simulation results prove that the junction temperature of the new structure is 10.17 °C lower than that of the conventional structure. Even if the CFC-LED has 24 Au bumps, the thermal resistance of the new structure is still far less than that of the conventional structure. The SFC-LED has a better thermal property.

Comparison of the properties of AlGaInN light-emitting diode chips of vertical and flip-chip design using silicon as the a submount

Vertical and flip-chip light-emitting diode (LED) chips are compared from the viewpoint of the behavior of current spreading in the active region and the distribution of local temperatures and thermal resistances of chips. AlGaInN LED chips of vertical design are fabricated using Si as a submount and LED flipchips were fabricated with the removal of a sapphire substrate. The latter are also mounted on a Si submount. The active regions of both chips are identical and are about 1 mm2 in size. It is shown that both the emittance of the crystal surface in the visible range and the distribution of local temperatures estimated from radiation in the infrared region are more uniform in crystals of vertical design. Heat removal from flip-chips is insufficient in regions of the n contact, which do not possess good thermal contact with the submount. As a result, the total thermal resistances between the p-n junction and the submount both for the vertical chips and for flip-chips are approximately 1 K/W. The total area of the flip-chips exceeds that of the vertical design chips by a factor of 1.4.

Analysis of thermal properties of GaInN light-emitting diodes and laser diodes

The thermal properties, including thermal time constants, of GaInN light-emitting diodes (LEDs) and laser diodes (LDs) are analyzed. The thermal properties of unpackaged LED chips are described by a single time constant, that is, the thermal time constant associated with the substrate. For unpackaged LD chips, we introduce a heat-spreading volume. The thermal properties of unpackaged LD chips are described by a single time constant, that is, the thermal time constant associated with the heat spreading volume. Furthermore, we develop a multistage RthCth thermal model for packaged LEDs. The model shows that the transient response of the junction temperature of LEDs can be described by a multiexponential function. Each time constant of this function is approximately the product of a thermal resistance, Rth, and a thermal capacitance, Cth. The transient response of the junction temperature is measured for a high-power flip-chip LED, emitting at 395 nm, by the forward-voltage method. A two stage RthCth model is used to analyze the thermal properties of the packaged LED. Two time constants, 2.72 ms and 18.8 ms are extracted from the junction temperature decay measurement and attributed to the thermal time constant of the LED GaInN/sapphire chip and LED Si submount, respectively.

GaN-Based Power Flip-Chip LEDs With Cu Submount

Nitride-based power flip-chip (FC) LEDs with Cu submount were proposed and prepared. With a much higher thermal conductivity, it was found that we can achieve a lower operation voltage under high-current injections and lower junction temperature from the FC LEDs with Cu submount. Compared with the power FC LEDs with Si submount, the reliability of the proposed device was also better.

Mounting-induced strains in red-emitting (Al)InGaP laser diodes tuned by pressure

The hydrostatic pressure behavior of red-emitting diode lasers packaged on Si, AlN, and diamond submounts is studied in the 0–2 GPa range by emission and photocurrent spectroscopy. Photocurrent spectroscopy allows for simultaneous measurement of the InGaP quantum well and (Al0.5Ga0.5)0.5In0.5P waveguide. A broadening of the absorption edge of the waveguide is observed for all devices and explained by the pressure-induced direct-to-indirect transition in this material. For the QW resonance, distinct differences are observed for differently packaged devices. Thus, very low pressure tuning rates are demonstrated for devices packaged on diamond and AlN submounts and explained by the presence of shear strain components. Consistently we find the device packaged on Si to be least affected by the strain caused by the pressure cycling.

Nitride-based high power flip-chip near-UV LEDs with reflective submount

Nitride-based high power flip-chip near-ultraviolet (UV) light emitting diodes (LEDs) with a reflective mirror are fabricated by depositing Al onto a Si submount. It is demonstrated that the Al layer coated onto a Si submount can effectively reflect downward emitting photons for flip-chip LEDs. Although the operation voltage of the proposed LEDs is slightly increased, it is found that the output power is at least 30% higher than that of conventional LEDs. It is also found that flip-chip near-UV LEDs are more reliable than conventional non-flip-chip LEDs.

High power ultraviolet light emitting diodes based on GaN∕AlGaN quantum wells produced by molecular beam epitaxy

In this paper, we report on the growth by molecular beam epitaxy and fabrication of high power nitride-based ultraviolet light emitting diodes emitting in the spectral range between 340 and 350nm. The devices were grown on (0001) sapphire substrates via plasma-assisted molecular beam epitaxy. The growth of the light emitting diode (LED) structures was preceded by detailed materials studies of the bottom n-AlGaN contact layer, as well as the GaN∕AlGaN multiple quantum well (MQW) active region. Specifically, kinetic conditions were identified for the growth of the thick n-AlGaN films to be both smooth and to have fewer defects at the surface. Transmission-electron microscopy studies on identical GaN∕AlGaN MQWs showed good quality and well-defined interfaces between wells and barriers. Large area mesa devices (800×800μm2) were fabricated and were designed for backside light extraction. The LEDs were flip-chip bonded onto a Si submount for better heat sinking. For devices emitting at 340nm, the measured differential on-series resistance is 3Ω with electroluminescence spectrum full width at half maximum of 18nm. The output power under dc bias saturates at 0.5mW, while under pulsed operation it saturates at approximately 700mA to a value of 3mW, suggesting that thermal heating limits the efficiency of these devices. The output power of the investigated devices was found to be equivalent with those produced by the metal-organic chemical vapor deposition and hydride vapor-phase epitaxy methods. The devices emitting at 350nm were investigated under dc operation and the output power saturates at 4.5mW under 200mA drive current.

Epoxyless Fiber-to-Submount Bonding for Active Fiber Optoelectronic and Fiber Backplane Applications

A fiber-coupled optical transmitter or receiver is both a mechanical and an optical system. Packaging of optical components like fiber-coupled lasers requires good coupling into the fiber, and rigid inflexible mounting of all components, so the coupling remains stable over the multiyear lifetime expected of optoelectronic components. In this paper, we report a new technique for bonding fiber directly to a Si or glass submount for autoaligned direct fiber attachment, based on field-assisted anodic or cathodic bonding. Under the influence of an electric field at high temperature, oxides are formed between the glass and the metal: this method is used to bond both metallized fibers to a glass V-groove (cathodic bonding), and glass fibers to a metallized Si submount (anodic bonding), without epoxy. Typical shear strengths are >300 g, comparable to solder-mounted components. The V-grooves precisely align the fiber to the component in two of the three dimensions. The thermal stability of this technique is demonstrated through showing <0.1 dB variation in coupling between two bonded fibers in aV-groove over a temperature range of 25degC-85degC. This method of fiber attachment is a robust and economical way to attach fibers for passive alignment and direct butt-coupling between the fiber and the semiconductor laser, receiver, or other optoelectronic component

A Novel Technique for High-Strength Direct Fiber-to-Si Submount Attachment Using Field-Assisted Anodic Bonding for Optoelectronics Packaging

A large portion of the cost for commercial fiber-coupled optoelectronics is packaging. Developments which reduce packaging time, eliminate components, and improve packaging automation can have an enormous impact in reducing cost and increasing availability of packaged lasers and receivers. One key step for fiber-coupled devices is alignment of the fiber to the device and rigid attachment of the fiber. In this letter, we present a new technique for bonding fiber autoaligned directly to an active device or waveguide on a Si-submount using field-assisted anodic bonding. Silica fibers coated with a high-Na+ glass (through sputtering of Pyrex, or coating and curing with liquid sodium silicate solution) are placed in a metallized v-groove on the Si submount and anodically bonded. This bond has shear strength comparable to solder-bonded components (>600 g) and the v-groove autoaligns the fiber to the component in two of the three dimensions. This novel combination of anodic bonding and coated fiber on precision fabricated v-grooves eliminates lenses and packaging time, will lead to lower-cost packages, and will facilitate multicomponent optical submounts and other novel optoelectronic technology.

Microstructure and Strain in GaAs/AlGaAs MQW thin Films Bonded to Different Substrates by Eutectic Alloying

AbstractResearch of the strain effect on semiconductors and their heterostructures has generated increasing interests due to its important device applications. We have developed a eutectic bonding technique to create in-plane anisotropic strain in GaAs/AlGaAs multiple quantum well (MQW) thin films. MQW thin films grown on (100) GaAs substrates were bonded to (100) GaAs, (100) Si and Y-cut LiNbO3 submounts with a Au/Sn eutectic alloy. The bonding materials consist of Au/Sn multilayer (80 wt% Au and 20 wt% Sn; 0.95μm) with a Cr (500Å) adhesion layer. The bonding process was optimized by carefully choosing the annealing conditions. After bonding, the substrates of the MQWs were removed by wet chemical etching. The in-plane strain was induced in MQW thin film due to the different thermal expansion between the thin film and submount. The strain was characterized using X-ray rocking curve. The microstructures of bonding interfaces and MQW thin films were examined by scanning electron microscope(SEM) and cross-section transmission electron microscope (XTEM). This bonding technique can be used for many new device applications which take the advantage of in-plane strain, as well as for device integration.

Selfaligned fibre pigtailed surface emitting lasers on Si submounts

A selfaligned packaging technique using Si submounts for potentially low cost fabrication of discrete and array fibre pigtailed surface emitting lasers is reported. Essentially 100% coupling efficiency and more than 0.5 mW output power multimode fibre pigtailed laser packages were demonstrated.

Stress compensation in laser diodes

Stress compensation in GaAs-(Ga,Al)As laser diodes is discussed. The stress distributions in the laser diodes are theoretically simulated by the finite element method. The photoelastic effect is used to observe the actual strain fields. It is found by simulation that the stress can be minimized by optimizing the Si submount thickness. Lasers fabricated with the optimized submount successfully exhibit low strain fields.

A closely spaced (50 μm) array of 16 individually addressable buried heterostructure GaAs lasers

An array of 16 individual addressable lasers with 50-μm center spacing has been monolithically integrated on a GaAs chip and cw bonded to a Si submount and copper heat sink. The lasers have the loss stabilized buried heterostructure geometry with separate optical and carrier confinement. The advantages of this laser geometry for integration into arrays are described.

Single-mode junction-up TJS lasers with estimated lifetime of 106hours

Accelerated life test for single-mode junction-up TJS lasers have been carried out at ambient temperatures of 50, 60, 70, 80, and 90°C. The laser chips are passivated with Si 3 N 4 films and die bonded on Si submounts. Estimated mean time to failure is 106h at 25°C.