Investigation of Wafer Level Packaging schemes for 3D RF interposer multi-chip module

Abstract

Abstract Very small RF modules can be realized through heterogenous integration of GaAs MMIC (monolithic microwave integrated circuit) onto a low loss Si sub-mount, with high density routing lines realized by advanced patterning. In this paper we investigate how to integrate MMIC active devices on GaAs with the RF passives produced on an interposer, using Si wafer process technology. High resistive Silicon substrates are required to minimize RF losses. The interposer is thinned below 100 μm to reveal Cu TSVs from the back of the interposer, while the front side is covered entirely with a silicon capping wafer for shielding the device. We compare different wafer level packaging approaches for producing the low RF-loss interposers, and populating them using die-to-die (D2D) or die-to-wafer (D2W) bonding of the MMIC components, followed by wafer level encapsulation. Two D2W approaches are compared, in the first approach the D2W mounting and the encapsulation happens before the Si interposer is thinned for TSV reveal. To avoid damage during thinning of the wafer, thicker substrates with deeper TSV of 150 μm or more are required. In a second approach, the thinning of the interposer is done prior to the mounting. Initial electrical data showed that the approach yielded proper RF performance, but further yield optimization is required.