Wafer level encapsulation - a transfer molding approach to system in package generation

Abstract

Flip chip and wafer level CSP technology have been widely accepted as a means for maximum miniaturization. Both package types do not generally include an explicit encapsulation layer, but only die passivation and dielectric rewiring layers respectively. To fulfill the reliability demands of harsh environment applications, the use of an additional encapsulant is recommended. Processes for wafer level encapsulation include wafer level molding and wafer level liquid encapsulation, both bearing individual advantages and disadvantages. Within this paper both, high precision, high volume transfer molding and the rather low cost wafer level printing have been investigated, focusing on the feasibility of reliable wafer encapsulation and the suitability of current materials. This paper presents the process development and feasibility of transfer molding as wafer level encapsulation technology for single die packages as well as for SIP solutions.