Si Stack Research Articles

Unprecedented Uniform 3D Growth Integration of 10-Layer Stacked Si Nanowires on Tightly Confined Sidewall Grooves.

Bottom-up catalytic growth offers a high-yield, versatile, and powerful tool for the construction of versatile 3D nanocomplexes, while the major challenge is to achieve a precise location and uniformity control, as guaranteed by top-down lithography. Here, an unprecedented uniform and reliable growth integration of 10-layer stacked Si nanowires (SiNWs) has been accomplished, for the very first time, via a new groove-confined and tailored catalyst formation and guided growth upon the truncated sidewall of SiO2/SiNx multilayers. The SiNW array accomplishes a narrow diameter of Dnw = 28 ± 2.4 nm, NW-to-NW spacing of tsp = 40 nm, and extremely stable growth over Lnw > 50 μm and bending locations, which can compete with or even outperform the state-of-the-art top-down lithography and etching approaches, in terms of stacking number, channel uniformity at different levels, fabrication cost, and efficiency. These results provide a solid basis to establish a new 3D integration approach to batch-manufacture various advanced electronic and sensor applications.

Hetero-Interfacial Thermal Resistance Effects on Device Performance of Stacked Gate-All-Around Nanosheet FET

This article reports that Hetero-interfacial-thermal resistance (HITR) due to phonon scattering and weak electron–phonon coupling at hetero-interfaces, can impact stacked Si gate-all-around (GAA) nanosheet field effect transistor (NSHFET) self-heating effect (SHE) and reliability. We have investigated the HITR of Si/SiO2 and Si/metal-silicides on SHE of vertically stacked Si GAA NSHFET. Our simulation predictions reveal that a very noticeable effect of the HITR of Si/ M0 at front end of line (FEOL) and back end of line (BEOL) interface (FEOL/BEOL) is that the hot-spot location is shifted into the channel away from drain depletion region, which affects the device SHE and degrades device performance. The impact of nanosheet width ( ${W}_{NSH}$ ) and sheets stacking number ( ${N}$ ) on device SHE and drive current degradation with and without HITR effect are also studied. It is revealed that wider nanosheets with lower HITR can be a better device design choice for heat mitigation in high performance logic transistors.

Single step bonding of thick anodized aluminum oxide templates to silicon wafers for enhanced system-on-a-chip performance

Vertically-aligned nanostructures are of interest for novel system-on-a-chip applications including sensing and energy storage. Templated synthesis of such structures has been previously demonstrated via anodized aluminum oxide (AAO). However, the performance of AAO-on-Si devices has been limited by current methods of obtaining well-adhered, thick AAO templates on Si substrates. Thicker AAO templates allow for longer nanostructures of active material, which is expected to increase performance of devices reliant on the surface area or volume of the active material. In this study, Al–Si eutectic bonding is used to achieve thick AAO-on-Si, with templates up to 90 μm thick bonded to the wafer. Carbon nanotubes (CNTs) are grown in the AAO templates bonded to Si to create proof-of-concept on-chip electrochemical double layer capacitors (EDLC) devices. Our devices show a promising value of 0.44 mF cm−2, much higher than previous AAO capacitors on Si chips. The structure of the CNT/AAO/Al/Si stack is examined using SEM and TEM, and the device performance is tested through cyclic voltammetry (CV), electrochemical impedance spectroscopy (EIS), and galvanostatic charge-discharge (GCD) measurements.

On the [formula omitted]-detection efficiency of a combined Si and plastic stack detector for DESPEC

A Geant4 simulation has been carried out in order to determine the β-detection efficiency of a rare isotope beam implantation setup, for decay spectroscopy experiments, comprising a number of Double Sided Silicon Strip Detectors (DSSSDs) and two plastic scintillation detectors placed upstream and downstream. The absolute efficiency for the emitted β-particle detection from radioactive fragments implanted in the DSSSDs using fast-timing plastic-scintillator detector, is calculated. The detection efficiency of the setup has been studied with two different distances between the Si layers and plastics. The requirement for the thickness of the Si detector layers and its implication on the β-detection efficiency has been investigated for 1 mm and 300μm thickness of Si layers. The combined efficiency of DSSSD and plastic detectors were also simulated for two different thicknesses of the DSSSD.

Electroplated Ru and RuCo films as a copper diffusion barrier

Thin, stacked films of Cu (1 μm)/RuxCo1-x(100 nm) were deposited on textured NiSiy/Si by electroplating. The Cu/RuxCo1-x/NiSiy/Si structure was then annealed at temperatures of 300–800 °C to evaluate the thermal stability. The structures of Cu/RuxCo1-x/NiSiy/Si characterized by scanning electron microscopy (SEM), scanning transmission electron microscope (STEM), energy dispersive X-ray spectrometer (EDS), and powder X-ray diffraction (XRD). The results demonstrated that the Cu/RuxCo1-x/NiSiy/Si stack could be maintained up to 400 °C. For the Cu/RuxCo1-x/NiSiy/Si stack with x = 0.9–0.6 sample, the diffusion of Cu atoms into the silicon substrate was effectively suppressed. However, the copper atom diffusion into silicon can be found at Cu/Ru/NiSiy/Si sample at a temperature of 400 °C. The pure ruthenium thin film as a diffusion barrier to copper is limited. The RuCo barrier is ascertained to be a more robust barrier for copper diffusion than the Ru barrier. It can be attributed to the addition of Co in Ru thin film, which reduces the copper atoms to penetrate the silicon substrate.

Vertical Leakage in GaN-on-Si Stacks Investigated by a Buffer Decomposition Experiment

We investigated the origin of vertical leakage and breakdown in GaN-on-Si epitaxial structures. In order to understand the role of the nucleation layer, AlGaN buffer, and C-doped GaN, we designed a sequential growth experiment. Specifically, we analyzed three different structures grown on silicon substrates: AlN/Si, AlGaN/AlN/Si, C:GaN/AlGaN/AlN/Si. The results demonstrate that: (i) the AlN layer grown on silicon has a breakdown field of 3.25 MV/cm, which further decreases with temperature. This value is much lower than that of highly-crystalline AlN, and the difference can be ascribed to the high density of vertical leakage paths like V-pits or threading dislocations. (ii) the AlN/Si structures show negative charge trapping, due to the injection of electrons from silicon to deep traps in AlN. (iii) adding AlGaN on top of AlN significantly reduces the defect density, thus resulting in a more uniform sample-to-sample leakage. (iv) a substantial increase in breakdown voltage is obtained only in the C:GaN/AlGaN/AlN/Si structure, that allows it to reach VBD > 800 V. (v) remarkably, during a vertical I–V sweep, the C:GaN/AlGaN/AlN/Si stack shows evidence for positive charge trapping. Holes from C:GaN are trapped at the GaN/AlGaN interface, thus bringing a positive charge storage in the buffer. For the first time, the results summarized in this paper clarify the contribution of each buffer layer to vertical leakage and breakdown.

(Invited) Vertically Stacked n Channel and p Channel Transistors

The Si FinFET architecture has been used in mass production in the industry for several technology nodes. Recently, the horizontal stacked channel GAAFET becomes a good candidate to achieve better power-performance properties than FinFETs in a certain area due to the promise of well controlled epitaxy, selective etching, and GAA nature. The state-of-the-art stacked Si channel n/pGAAFETs and stacked Ge channel pGAAFETs have been reported. In this study, we demonstrate the CVD grown, vertically-stacked strained GeSi channels for nGAAFETs and GeSn channels for pGAAFETs. The stacked GeSi nGAAFETs provide a possible solution to improve the electrostatics for Ge-based channel GAAFETs while the stacked GeSn pGAAFETs has record high ION and Gm with highly competitive subthreshold behaviors among GeSn pFinFETs and pGAAFETs. In addition, record low contact resistivity (4.4x10-10 ohm-cm2) to Ge using in-situ B and Sn incorporation by CVD is also demonstrated with low thermal budget (≦400oC) and without any Ga doping. The Ge/Ge0.85Si0.15 and Ge/Ge0.91Sn0.09 multi layers are epitaxially grown on SOI substrates by CVD. Ge buffer layers and sacrificial layers are not only used to be selectively etched in preference to GeSi and GeSn to form the vertical stacked GeSi channels and GeSn channels, but also to stress both GeSi N-channels tensily and GeSn P-channels compressively, respectively. The high temperature anneal for the buffer can confine the dislocations at the bottom of Ge buffer and reduce the defect density in the channels to improve the device performance. The heavy in-situ doping of source and drain, post metal annealing, laser annealing for nFETs, and NiGe/ PtGeSn formation can reduce the parasitic resistance to reveal the intrinsic merit of the high mobility GeSi and GeSn channels. For GeSi nFETs, rhe △Ec between GeSi and Si is nearly zero. As a result, electron can flow through stacked GeSi channels and Si channel underneath for the nFETs. The Vt difference between GeSi and Si can be tuned by the channel size optimizing. By narrowing the GeSi channel size to 5nm, the bandgap can be increased by quantum confinement and the short channel effect can be suppressed. As a result, more positive Vt for GeSi than Si is observed. The Si channel turn on first with good SS=76mV/dec and DIBL=36mV/V due to low Dit and good short channel control. Ioff is also dramatically reduced and the Ion/Ioff are improved to be 1.2E7 thanks to the increase of the bandgap and the improved short channel control for the narrow GeSi channels. The improved flicker noise also indicates the enhanced reliability. For GeSn pFETs, the {111} plane has high mobility, low dangling bond density, low Dit, and better gate control than the rectangular channel. Vertically stacked triangular Ge0.91Sn0.09 pGAAFETs with compressive strain of ~2% in the channel and low surface roughness are achieved by orientation dependent etching on natural etching stop {111} plane by the optimized etching process. The 22% reduction of SSlin=84mV/dec, 50% improvement of ION=120mA/mm at VOV=VDS=-0.5V, and 71% improvement of Gm=312mS/mm at VDS=-0.5V are achieved as compared to our previous work of 3 stacked Ge0.93Sn0.07 nanosheets. The device has the record ION of 19.3mA per stack at VOV= VDS=-0.5V and record Gm,max of 50.2mS per stack at VDS=-0.5V with competitive subthreshold behaviors among GeSn pFinFETs and pGAAFETs. For the p-type contact resistivity (ρc) reduction, B (>1x1021cm-3) and Sn (>12%) segregations at the Ti/GeSn:B interface are used to reduce the hole tunneling distance and the Schottky barrier height of holes, respectively. The GeSn:B is grown by CVD using Ge2H6, SnCl4, and B2H6 in H2 ambient at ≦320oC. Due to the Sn segregation, there is no need to grow high-[Sn] GeSn layer for the ρc reduction, which makes the pseudomorphic growth of the compressively strained GeSn possible. After metal deposition at elevated temperature and 400oC annealing, the ρc of 4.4x10-10 ohm-cm2 is achieved. Ge nGAAFETs, GeSn pGAAFETs, and the S/D with extremely low contact resistivity fabricated by CVD growth and optimized process are compatible with Si technologies and becomes promising candidates for CMOS applications in the future technology nodes. Acknowledgements: The MOST (107-2218-E-002-044-, 107-2622-8-002-018) and MOE (NTU-CC-108L891701), Taiwan. The support from Taiwan Semiconductor Research Institute is also highly appreciated.

Improved Endurance of HfO2-Based Metal- Ferroelectric-Insulator-Silicon Structure by High-Pressure Hydrogen Annealing

We investigate the effects of high-pressure hydrogen annealing (HPHA) on W/ferroelectric Al:HfO2/interface layer (IL)/Si stacks. With HPHA, degradation in remnant polarization is observed in the pristine state due to ferroelectric domain pinning. However, after wake-up, a comparable remnant polarization is observed by domain de-pinning. In addition, HPHA improves the quality current and low interface trap density are maintained up to 107 cycles. As a result, the endurance improves up to 109 cycles and a stable retention is achieved up to 104 s at 85 °C. These results show that the HPHA can be a crucial process for ferroelectric HfO2-based transistor applications.

Ferroelectric ZrO2 Monolayers as Buffer Layers between SrTiO3 and Si

A monolayer of ZrO$_{2}$ has recently been grown on the Si(001) surface and shown to have ferroelectric properties, which signifies the realization of the lowest possible thickness in ferroelectric oxides [M. Dogan et al., Nano Lett., 18 (1) (2018)]. In our previous computational study, we reported on the multiple (meta)stable configurations of ZrO$_{2}$ monolayers on Si, and how switching between a pair of differently polarized configurations may explain the observed ferroelectric behavior of these films [M. Dogan and S. Ismail-Beigi, arXiv:1902.01022 (2019)]. In the current study, we conduct a DFT-based investigation of (i) the effect of oxygen content on the ionic polarization of the oxide, and (ii) the role of zirconia monolayers as buffer layers between silicon and a thicker oxide film that is normally paraelectric on silicon, e.g. SrTiO$_{3}$. We find that (i) total energy-vs-polarization behavior of the monolayers, as well as interface chemistry, is highly dependent on the oxygen content; and (ii) SrTiO$_{3}$/ZrO$_{2}$/Si stacks exhibit multiple (meta)stable configurations and polarization profiles, i.e. zirconia monolayers can induce ferroelectricity in oxides such as SrTiO$_{3}$ when used as a buffer layer. This may enable a robust non-volatile device architecture where the thickness of the gate oxide (here strontium titanate) can be chosen according to the desired properties.

Piezoelectric Pressure Sensors for Hypersonic Flow Measurements

A microelectromechanical-system piezoelectric pressure sensor targeting hypersonic flow applications is presented. The sensing diaphragms have 500- $\mu \text{m}$ diameter and are comprised of a composite stack of Si, SiO2, and AlN. This paper presents the fabrication and packaging details of the sensor and then presents test results from a Mach-6 hypersonic-flow facility, in which the prototype sensor data are compared against data from a mature commercial sensor present in the same tests. Salient hypersonic-flow features are observed in signals captured by the prototype. The package is comprised of an on-chip two-element array with 650- $\mu \text{m}$ pitch, and signals from the elements captured during hypersonic-flow tests are highly correlated. [2018-0196]

Lithium ion trapping mechanism of SiO2 in LiCoO2 based memristors

Pt/LiCoO2/SiO2/Si stacks with different SiO2 thicknesses are fabricated and the influence of SiO2 on memristive behavior is investigated. It is demonstrated that SiO2 can serve as Li ion trapping layer benefiting device retention, and the thickness of SiO2 must be controlled to avoid large SET voltage and state instability. Simulation model based on Nernst potential and diffusion potential is postulated for electromotive force in LiCoO2 based memristors. The simulation results show that SiO2 trapping layer decreases the total electromotive field of device and thereby prevents Li ions from migrating back to LiCoO2. This model shows a good agreement with experimental data and reveals the Li ion trapping mechanism of SiO2 in LiCoO2 based memristors.

Synaptic behaviors of HfO2 ReRAM by pulse frequency modulation

A resistive switching random-access memory (ReRAM) device with TiN/HfO2/SiO2/p+-Si stack is analyzed for synaptic behavior. Fabricated RRAM device stack consists of heavily doped p-type silicon bottom electrode (BE), HfO2 as a switching layer, SiO2 as a tunneling barrier layer and TiN as a top electrode (TE). The RRAM cell successfully shows I-V curves including SET and RESET operations in DC sweep mode. By inserting a SiO2 tunneling barrier layer, gradual switching characteristics are obtained by pulse operation. By optimizing the pulse scheme applied to the device, biological synaptic plasticity of long-term potentiation and depression is demonstrated. Finally, spike rate-dependent plasticity (SRDP) learning rule is realized by applying pulses with different frequencies to both terminals of the ReRAM device.

Modulation of resistive switching in Pt/LiCoO2/SiO2/Si stacks

Pt/LiCoO2/SiO2/Si stacks are fabricated by pulsed laser deposition and annealed at different annealing temperature. Pt/LiCoO2/SiO2/Si stacks exhibit lower current and higher high resistance state/low resistance state ratio than other stacks with homogeneous resistive switching. It is found that resistive switching behavior of Pt/LiCoO2/SiO2/Si stacks can be modulated by LiCoO2 crystal structures. The Pt/LiCoO2/SiO2/Si stacks with R-3m LiCoO2 phase show larger maximum currents and better state stability than samples with amorphous LiCoO2, and samples with amorphous or R-3m LiCoO2 phase exhibit non-homogeneous or homogeneous resistive switching, respectively. The reasons for the different resistive switching behaviors are investigated and discussed. These findings provide insights into how to improve the performance of Pt/LiCoO2/SiO2/Si stacks and a further understanding of the homogeneous resistive switching behavior.

Evaluation of the potential distribution in a multiple stacked Si quantum dots structure by hard X-ray photoelectron spectroscopy

Six-fold stacked Si quantum dots (Si-QDs) structures with ultrathin SiO2 interlayers were formed on ultrathin SiO2 layer/n-Si substrates by low-pressure chemical vapor deposition using a SiH4 gas and their vertical electric potential distributions were evaluated using hard X-ray photoelectron spectroscopy under a DC bias application to the semitransparent electrodes formed on the stacked Si-QDs structure. The Si1s photoelectron spectra due to Si–Si bonding units can be deconvoluted into seven components corresponding to the six Si-QDs layers and Si substrate. Obviously, the energy shift between the components for two adjacent dots layers becomes larger towards the upper side of the stacked dots structure. This result indicates that the electric field concentrates on the upper side and is consistent with the proposed model that can explain the ballistic electron emission characteristics from multiple stacked Si-QDs structures.

Effects of annealing temperature on workfunction of MoOx at MoOx/SiO2 interface and process-induced damage in indium tin oxide/MoOx/SiOx/Si stack

The workfunction of molybdenum oxide (MoOx) at the MoOx/SiO2 interface, which is referred to as the interface workfunction, and the process-induced damage at the SiO2/Si interface in an indium tin oxide (ITO)/MoOx/SiO2/Si structure are extracted by capacitance–voltage (C–V) analysis. The estimated interface workfunction is compared with that of the bulk determined by ultraviolet photoelectron spectroscopy (UPS). The interface workfunction of 5.59 eV for the as-grown ITO condition is 0.41 eV smaller than the bulk workfunction for the as-grown MoOx film. The reactive-plasma deposition (RPD) process induces damage at the SiO2/Si interface, with an estimated interface defect density (Dit) of 3.9 × 1011 cm−2 eV−1. The effects of postdeposition annealing in a forming gas on these parameters are also studied. The interface workfunction decreases with increasing temperature to 5.24 eV at 400 °C, while that of the bulk is 5.9 eV, suggesting a difference in the interface and bulk properties. The damage is almost removed at 250 °C.

Multi-layer MOS capacitor based polarization insensitive electro-optic intensity modulator.

In this study, a multi-layer metal-oxide-semiconductor capacitor (MLMOSC) polarization insensitive modulator is proposed. The design is validated by numerical simulation with commercial software LUMERICAL SOLUTION. Based on the epsilon-near-zero (ENZ) effect of indium tin oxide (ITO), the device manages to uniformly modulate both the transverse electric (TE) and the transverse magnetic (TM) modes. With a 20μm-long double-layer metal-oxide-semiconductor capacitor (DLMOSC) polarization insensitive modulator, in which two metal-oxide-semiconductor (MOS) structures are formed by the n-doped Si/HfO2/ITO/HfO2/ n-doped Si stack, the extinction ratios (ERs) of both the TE and the TM modes can be over 20dB. The polarization dependent losses of the device can be as low as 0.05dB for the "OFF" state and 0.004dB for the "ON" state. Within 1dB polarization dependent loss, the device can operate with over 20dB ERs at the S, C, and L bands. The polarization insensitive modulator offers various merits including ultra-compact size, broadband spectrum, and complementary metal oxide semiconductor (CMOS) compatibility.

Enhanced Performance of ITO-Assisted Electro-Absorption Optical Modulator Using Sidewall Angled Silicon Waveguide

The balance between extinction ratio and insertion loss is a stringent condition while realizing efficient optical modulators with a higher figure-of-merit (FOM), lower power consumption, and wider modulation bandwidth. The higher value of FOM is associated with the requirement of a larger extinction ratio and a smaller insertion loss. In the model presented here, the balance between the extinction ratio and insertion loss is maintained by the device architecture and choosing ON-state of the modulator at a lower carrier concentration regime. An electroabsorption (EA) optical modulator architecture comprised of Si/HfO2/ITO/Si stack upon a silica substrate offers an extinction ratio of 6.81 dB/μm, insertion loss of 0.019 dB/μm, and FOM of 337. The modulation bandwidth is as high as 78.85 GHz with active 3-dB length of 440 nm at the expense of 20 f J/bit. The optical bandwidth is excess of 220 nm operating between ∼1440 and ∼1660 nm.

Ferroelectric HfZrOx-based MoS2 negative capacitance transistor with ITO capping layers for steep-slope device application

A negative capacitance field-effect transistor (NCFET) built with hafnium-based oxide is one of the most promising candidates for low power-density devices due to the extremely steep subthreshold swing (SS) and high on-state current induced by incorporating the ferroelectric material in the gate stack. Here, we demonstrated a two-dimensional (2D) back-gate NCFET with the integration of ferroelectric HfZrOx in the gate stack and few-layer MoS2 as the channel. Instead of using the conventional TiN capping metal to form ferroelectricity in HfZrOx, the NCFET was fabricated on a thickness-optimized Al2O3/indium tin oxide (ITO)/HfZrOx/ITO/SiO2/Si stack, in which the two ITO layers sandwiching the HfZrOx film acted as the control back gate and ferroelectric gate, respectively. The thickness of each layer in the stack was engineered for distinguishable optical identification of the exfoliated 2D flakes on the surface. The NCFET exhibited small off-state current and steep switching behavior with minimum SS as low as 47 mV/dec. Such a steep-slope transistor is compatible with the standard CMOS fabrication process and is very attractive for 2D logic and sensor applications and future energy-efficient nanoelectronic devices with scaling power supply.

Fermi-level pinning in full metal/high-k/SiO2/Si stacks

Fermi-level pinning (FLP) in full Metal/High-k/SiO2/Si stacks is investigated based on the improved electron state density (IESD) model. The SiO2 interlayer between the high-k layer and Si and the effects of the high-k/SiO2/Si interface on FLP are analyzed. The effective work function (EWF) is influenced by the density of states in high-k/SiO2/Si stacks with the exception of the effects of the electron state density in the metal gate. The IESD model provides physical insights and is a simple and convenient method to calculate the EWF of MOS devices with different types.

(Invited) MOS Interface Defect Control in Ge/III-V Gate Stacks

One of the most critical issues for realizing high performance Ge/III-V CMOS, which can be regarded as one of the promising device structures in the future technology nodes, is to establish the gate stack technologies simultaneously satisfying many requirements such as thin EOT, low interface state density (Dit), low slow trap density (Dtrap), high channel mobility and high gate insulator reliability. For this purpose, basic understanding of Ge/III-V MOS interfaces including physical origins of interface defects and the influence on channel mobility is indispensable. In order to realize low Dit, high channel mobility and thin EOT for Ge MOSFETs, we proposed an interfacial layer (IL) formation process employing ECR plasma post oxidation to form ultrathin GeOx through thin ALD Al2O3 [1, 2] or HfO2/Al2O3 [3]. By using the HfO2/Al2O3/GeOx/Ge gate stacks, Ge n- and p-MOSFETs (EOT of 0. 76 nm) with high electron (690 cm2/Vs) and hole (550 cm2/Vs) peak mobility were obtained. However, one of the most difficult challenges for the present GeOx-based ILs is the existence of high Dtrap [4, 5]. The slow traps can exist near GeOx/Ge interfaces, because the trapping characteristics are almost insensitive to the thickness of GeOx and Al2O3 [6]. Recently, inclusion of Y atoms into GeOx has been reported to effectively suppress Dtrap [7, 8]. We are currently working for the reduction in Dtrap by suing the ALD AlYO3/GeOx or Y2O3/GeOx interfaces [9, 10]. While the impact is still limited at present, further improvement in Dtrap is expected. For III-V MOS interface control, understanding of III-V MOS interface defects and establishment of the MOS interface defect control technologies have not been fully obtained yet. There still remain many issues, such as (1) higher Dit and Dtrap at InGaAs MOS gate stacks with Al2O3-based ILs than in Si and Ge MOS gate stacks (2) inferior MOS interface properties on Sb-based materials such as GaSb, GaAsSb and InGaSb (3) poor MOS gate stack reliability [5, 11, 12]. We studied the impact of ALD La2O3/InGaAs MOS interfaces on the performance of InGaAs MOSFETs. It was found that La2O3/InGaAs MOSFETs exhibit lower S. S. and lower carrier trapping properties, while have lower mobility than Al2O3/InGaAs MOSFETs because of higher fixed oxide charge density. Also, it was experimentally found that ALD La2O3 films with thermal budget lower than 300 oC have ferroelectricity in W/La2O3/InGaAs MOS and W/La2O3/W MIM structures. The steep slope characteristics due to the negative capacitance effect have been demonstrated in W/La2O3(15nm)/InGaAs MOSFETs [13]. We also found that BHF/HF pre-treatment is more effective for reduction of the fast interface state density at ALD Al2O3/InxGa1-xAs with higher In content (x=0.7 and 1) in comparison with conventional (NH4)Sy pre-treatment [14, 15]. It was suggested through the XPS analyses that the reduction in Dit is attributable to the dominance of As dangling bonds on Dit with higher In content and the effective passivation of oxygen atoms with these dangling bonds. For GaSb and GaAsSb MOS interface control, ultrathin InAs and InGaAs surface passivation layers have been found to be effective in reducing the fast interface state density [16, 17]. However, the detailed studies on further reduction in Dit and Dtrap and understanding of the relationship between the channel mobility and the interface properties are still strongly needed for Sb-based MOS devices. This work was partly supported by JST-CREST and the Grant in-Aid for Scientific Research through the MEXT (26249038). The authors would like to thank Drs. M. Yokoyama, H. Yamada and T. Yamamoto in Sumitomo Chemical Corporation, and Drs. M. Mitsuhara, H. Sugiyama, T. Hoshi and H. Yokoyama in NTT for their collaborations.