Si Nanowire Transistors Research Articles

Comprehensive mobility study of silicon nanowire transistors using multi-subband models

Spatial confinement is important in advanced More Moore devices, such as nanowire transistors (NWTs), where the basic charge transport properties must be revised beyond the bulk crystal assumptions. This work presents a comprehensive and general overview of the electron mobility in aggressively-scaled Si NWTs in order to demonstrate the effect of quantum confinement on this topic, establishing its dependence on numerous physical factors (shape, diameter, and orientation). The mobility evaluation makes use of a unique simulation framework and innovative multi-subband calculations of the scattering rates. We show that (1) the effect of surface roughness scattering is more pronounced at higher sheet densities, (2) ionized impurity scattering seriously degrades the mobility in highly-doped NWTs, and (3) the cross-section shape affects directly the subband parameters and the mobility, with the elliptical NWTs giving the best performance for the same cross-sectional area.

Theoretical Study for Carrier Transit Limited Performance of Gate-All-Around Si Nanowire Transistor by Time-Dependent Quantum Transport Simulation

Theoretically, the upper limit performance of nanoscale transistor should be limited by carrier transit time through the channel as the charge in channel cannot follow the gate voltage and the gate capacitance will show strong frequency dependence if the gate voltage varies faster than the carrier transit time. Currently, the operation frequency of nanoscale transistor is limited by the non-ideal factors such as parasitic effects, and it is far below the limit caused by carrier transit time. However, how good the transistor can be if one can minimize these non-ideal factors is still a problem, thus, it would be worth exploring its upper limit performance. In this article, time-dependent quantum transport simulation is performed to explore the carrier transit limited performance of the gate-all-around (GAA) Si nanowire transistor. By using the mode space approach, the 3-D time-dependent quantum transport equation is decoupled to a 2-D confinement problem and a 1-D transport problem, and then self-consistently solved with the Poisson’s equation. The transient characteristics of channel charge are investigated, and it shows the response time of channel charge is in the scale of 0.1 ps. The responses of channel charge and drain current to high-frequency gate voltages are simulated. The carrier transit limited performance including the frequency-dependent gate capacitance and transconductance, 3 dB bandwidth, and cutoff frequency, are calculated and discussed.

Transport spectroscopy from Hubbard bands of dopant-induced quantum dot array to one-dimensional conduction subband

Arrays of dopant-induced quantum dots (QDs) are promising candidates as quantum bit platforms. We have achieved quantum transport spectroscopy of a junctionless silicon (Si) nanowire transistor with dual physical channels with a diameter of 10 nm fabricated by novel femtosecond laser projection exposure together with thermal oxidation. The spectroscopy demonstrates the evolution of the quantum transport process from Hubbard bands of dopant-induced QD array to one-dimensional (1D) conduction subbands. Eight pairs of current splitting peaks were observed at the initial stage of the drain current, representing the upper and lower Hubbard bands formed by the coupling of eight QDs. The current oscillation peaks in the 1D conduction subband elucidate the interference of reflected electron waves between the gate-defined barriers, which are proved by the mean wave vector interval matching the gate length. Our experimental results demonstrate the evolution of the quantum transport process in sub 10 nm dual Si channels with randomly doped dopant atoms, opening a new perspective for quantum states by dopant band engineering in Si nanoscale devices for scalable quantum computation.

Investigation of the cross-sectional morphology of epitaxial Si nanowires grown by chemical vapor deposition for the fabrication of vertical devices

The interfacial structure of Si nanowire transistors is decisively important to their electronic properties. Smooth sidewall surface of Si nanowires is therefore a prerequisite for the fabrication of vertical transistors. In this study, the axial cross-sectional morphology of epitaxial Si nanowires, which are grown vertically on Si[111] substrates by chemical vapor deposition via the vapour-liquid-solid mechanism, are analyzed by transmission electron microscopy to understand their surface morphology. It is noted that the cross-sections do not exhibit sharp facets. The roughness of the sidewall surface is attributed to precipitation of Si from AuSi liquid droplets. The cross-sectional shape of the Si nanowires is truncated-triangular, but not exactly symmetric. A larger distortion of the cross-sectional shape appears in tilted nanowires. It is also demonstrated that after removing the surface Au, post-growth oxidation of Si nanowires is helpful to rebuild smooth sidewall surface.

Electron transport via a few-dopant cluster in the presence of counter-dopants in silicon nanowire transistors

Electron transport through a few-donor cluster flanked by acceptors is studied by first-principles and semi-empirical simulations in gated Si-nanowire transistors with n + electrostatically-doped source/drain. Local density-of-states spectra are probed by electrical characteristics at room temperature for clarifying modifications induced by acceptor-atoms on the energy states of the few-donor cluster. It is found that acceptor-atoms located between the few-donor cluster and the leads mainly shift the cluster potential, introducing a minor distortion to its energy spectrum. The results change only weakly as the acceptor-atoms are moved towards the Si nanowire surface, and systematically depend on the number of acceptors.

A Quasi 2-D Electrostatic Potential and Threshold Voltage Model for Junctionless Triple Material Cylindrical Surrounding Gate Si Nanowire Transistor

A mathematical model used for determining the threshold voltage characteristics and electrostatic potential of a Junctionless Triple Material Cylindrical Surrounding Gate Silicon Nanowire Transistor (JLTMCSGSiNWT) is proposed in this research work and is obtained by resolving the poison equation. Three materials with dissimilar metal functions are used in the construction of the device gate structure. Device parameters used to determine the electrical characteristics are also included in the model. Behavior of the device is investigated through its vertical electrical field distribution along the device channel. Higher drain bias conditions leading to DIBL are reduced in the proposed structure by minimal variation of voltages owing to three different gate materials that maintain a steady field distribution along the channel. This model explicitly shows the impact of various criteria like drain bias voltage, gate bias voltage, thickness of the silicon layer, thickness of the oxide layer, and length of the channel on electrostatic potential and the deterioration of threshold voltage. The proposed analytical model is validated with TCAD simulations and it could be further extended to study the advanced electrical characteristics of the JL Triple Material CSG Silicon Nanowire Transistor.

Mobility of Circular and Elliptical Si Nanowire Transistors Using a Multi-Subband 1D Formalism

We have studied the impact of the cross-sectional shape on the electron mobility of n-type silicon nanowire transistors (NWTs). We have considered circular and elliptical cross-section NWTs including the most relevant multisubband scattering processes involving phonon, surface roughness, and impurity scattering. For this purpose, we use a flexible simulation framework, coupling 3D Poisson and 2D Schrodinger solvers with the semi-classical Kubo-Greenwood formalism. Moreover, we consider cross-section dependent effective masses calculated from tight binding simulations. Our results show significant mobility improvement in the elliptic NWTs in comparison to the circular one for both [100] and [110] transport directions.

Nanosized Metal-Grain-Granularity Induced Characteristics Fluctuation in Gate-All-Around Si-Nanowire Transistors at 1nm Technology Node

Nanosized Metal-Grain-Granularity Induced Characteristics Fluctuation in Gate-All-Around Si-Nanowire Transistors at 1nm Technology Node

Simulation of the Impact of Ionized Impurity Scattering on the Total Mobility in Si Nanowire Transistors.

Nanowire transistors (NWTs) are being considered as possible candidates for replacing FinFETs, especially for CMOS scaling beyond the 5-nm node, due to their better electrostatic integrity. Hence, there is an urgent need to develop reliable simulation methods to provide deeper insight into NWTs’ physics and operation, and unlock the devices’ technological potential. One simulation approach that delivers reliable mobility values at low-field near-equilibrium conditions is the combination of the quantum confinement effects with the semi-classical Boltzmann transport equation, solved within the relaxation time approximation adopting the Kubo–Greenwood (KG) formalism, as implemented in this work. We consider the most relevant scattering mechanisms governing intraband and multi-subband transitions in NWTs, including phonon, surface roughness and ionized impurity scattering, whose rates have been calculated directly from the Fermi’s Golden rule. In this paper, we couple multi-slice Poisson–Schrödinger solutions to the KG method to analyze the impact of various scattering mechanisms on the mobility of small diameter nanowire transistors. As demonstrated here, phonon and surface roughness scattering are strong mobility-limiting mechanisms in NWTs. However, scattering from ionized impurities has proved to be another important mobility-limiting mechanism, being mandatory for inclusion when simulating realistic and doped nanostructures, due to the short range Coulomb interaction with the carriers. We also illustrate the impact of the nanowire geometry, highlighting the advantage of using circular over square cross section shapes.

(Invited) Modelling and Simulation of Advanced Semiconductor Devices

I. Introduction Modeling and simulation of semiconductor devices have been a vital tool in driving the development and comprehensive understanding of the semiconductor physics and devices. In the last 4 decades’ analysis, using state-of-the-art device modeling tool has helped the process of miniaturization of MOSFET by characterizing their parameters, predicting their behavior on the system and circuit level. Additionally, modeling and simulation enhanced a deeper understanding of the critical issues surrounding the device scaling and its impact on overall system level functionality and reliability of its operation. To show their importance, in this paper, we present modeling and simulation of advanced semiconductor devices based on the realistic device structures. II. Model description The modeling of semiconductor devices is based on numerical solutions of a complex mathematical equation that describe their fundamental physical properties. In our TCAD tools, we use ranges of computational approaches. For example, we use the well-known and popular way of describing the carrier behavior, such as Drift Diffusion (DD) which can include Quantum Mechanical (QM) corrected models. Also in our work, we employ more computationally demanding methods such as Ensemble Monte Carlo (EMC) and Non-Equilibrium Green’s Function Formalism (NEGF) to simulate advanced atomistic devices where using the classical DD approach is not adequate to handle the quantum transport typical for the modern ultra-scaled transistors. Moreover, we perform a first principle (ab-initio) calculation from which one can extract physical parameters like band- gap and effective mass (m*) of electrons and holes to be used in the advanced modeling and simulation process. All the methods described above can evaluate the impact of various sources of statistical variability, random discrete dopants and their adverse impact on the device performance. III. Considered devices Advanced devices of current technology generations, such as FinFET and Silicon Nano Wire were born out of the necessity of continuing the scaling beyond the conventional MOSFET architecture. In this section, we present modeling and simulation of some of the existing important devices structures and new promising memory application devices. A. FinFET FinFET technology is massively adopted as the advanced logic node technology. Modeling and simulation of FinFETs and accurate predictions can significantly speed up the next technology node. 7nm technology node is a critical point due to its extremely complicated physics and technical difficulty in fabrication. Employing advanced TCAD tool is critically important in exploring the fundamental physical properties in the 7nm FinFET technology featured with Fin width of 5nm and height of 25nm. Accurate capturing of the charge distribution in the nanoscale channel is mandatory since the quantum effect plays a critical role regarding the performance. We achieved this by using solving 2D Poisson-Schrodinger equation in the cross-section of the device. The wave-functions in the corresponding sub-bands of each valley is calculated and the charge distribution is obtained for different gate biases. The profile of the charge distribution serves as the calibration target in the TCAD calibration tool for density-gradient coupled DD simulation. The calibration results provide accurate charge information for the further simulations. B. Z2FET Z2FET is one of the most complex structures, and yet very promising device to be used for application in a memory cell without connecting to extremal charge storage component (aka 1T-DRAM). Significant progress has been made in characterizing its memory behavior and analyzing its physical properties. These qualities can be exploited in the implementation of Z2FET in embedded 1T-DRAM application. To understand the complexity of this promising device, TCAD model is an invaluable asset. Although there are some experimental data that may help the characterization process, the use of numerical modeling is equally important in understanding the dynamics of carriers, how the DC operation of this device can be characterized in the different sections of the device. In this paper, we investigate the DC operation of Z2FET in conjunction with its memory behavior and how it can be used in 1-TDRAM memory cell. We present simulation based detail analysis of Z2FET in the main paper. C. Silicon Nano Wire Transistors Silicon nanowires have numerous potential applications, including transistors, memories, photovoltaics, biosensors and qubits. In this work, we demonstrate a solution by exploiting the quantum effects of a 1-Dimensional (1D) Si nanowire transistor and analyze 1D nanowires in a scalable, top-down Si technology.

Syringe-Injectable Electronics with a Plug-and-Play Input/Output Interface.

Syringe-injectable mesh electronics represent a new paradigm for brain science and neural prosthetics by virtue of the stable seamless integration of the electronics with neural tissues, a consequence of the macroporous mesh electronics structure with all size features similar to or less than individual neurons and tissue-like flexibility. These same properties, however, make input/output (I/O) connection to measurement electronics challenging, and work to-date has required methods that could be difficult to implement by the life sciences community. Here we present a new syringe-injectable mesh electronics design with plug-and-play I/O interfacing that is rapid, scalable, and user-friendly to nonexperts. The basic design tapers the ultraflexible mesh electronics to a narrow stem that routes all of the device/electrode interconnects to I/O pads that are inserted into a standard zero insertion force (ZIF) connector. Studies show that the entire plug-and-play mesh electronics can be delivered through capillary needles with precise targeting using microliter-scale injection volumes similar to the standard mesh electronics design. Electrical characterization of mesh electronics containing platinum (Pt) electrodes and silicon (Si) nanowire field-effect transistors (NW-FETs) demonstrates the ability to interface arbitrary devices with a contact resistance of only 3 Ω. Finally, in vivo injection into mice required only minutes for I/O connection and yielded expected local field potential (LFP) recordings from a compact head-stage compatible with chronic studies. Our results substantially lower barriers for use by new investigators and open the door for increasingly sophisticated and multifunctional mesh electronics designs for both basic and translational studies.

Influence of thermal losses at the gate contact of Si nanowire transistors: A phenomenological treatment in quantum transport theory

A quantum mechanical simulation approach relying on the non-equilibrium Green's function formalism, combining atomistic electron and phonon transport, and accounting for phonon losses at the gate contact is presented in this paper. To correctly capture self-heating effects in ultra-scaled gate-all-around nanowire field-effect transistors, it is necessary to go beyond electron-phonon and anharmonic phonon-phonon interactions. A phenomenological self-energy derived from Fourier's law is therefore introduced to model heat flows through oxide layers. It is found that in an NWFET with a channel length of 15 nm turning on thermal losses at the gate contact leads to a decrease in the maximum lattice temperature by more than 100 K and to a 10% increase in the device current in the ON-state.

Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit

In this work we investigate the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future CMOS applications at the scaling limit. For the purpose of this paper, we created Si NWTs with two channel crystallographic orientations 〈110〉 and 〈100〉 and six different cross-section profiles. In the first part, we study the impact of quantum corrections on the gate capacitance and mobile charge in the channel. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic performance of the NWTs, is also investigated. The influence of the rotating of the NWTs cross-sectional geometry by 90° on charge distribution in the channel is also studied. We compare the correlation between the charge profile in the channel and cross-sectional dimension for circular transistor with four different cross-sections diameters: 5nm, 6nm, 7nm and 8nm. In the second part of this paper, we expand the computational study by including different gate lengths for some of the Si NWTs. As a result, we establish a correlation between the mobile charge distribution in the channel and the gate capacitance, drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All calculations are based on a quantum mechanical description of the mobile charge distribution in the channel. This description is based on the solution of the Schrödinger equation in NWT cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions.

Ω-Gate Nanowire P-FET with cSiGe Channel Epitaxied on Strained-SOI Substrates

Introduction.Aggressively scaled Si NanoWire (NW) transistors have already been fabricated and their electrical properties assessed [1-3]. In order to further continue the Moore’s law, strain-induced performance enhancement is needed for both n and p type Field Effect Transistors (FETs). In a previous work, we demonstrated high-performance uniaxial tensely-strained NW n-type FETs down to 10nm gate length [4]. Symmetrically, compressively-strained SGOI [5-8] yielded improved short-channel performances for p-type FETs. In this work, we propose to integrate compressive SiGe (p-FETs) on strained-SOI substrates for a future hybrid CMOS integration with sSi channels for n-FETs and cSiGe channels for p-FETs. Devices Fabrication. The fabrication of NW p-FETs started with the epitaxy of 10nm thick Si0.7Ge0.3 films capped by 2nm of Si on 300mm s-SOI substrates (~1.4GPa biaxial tensile strain) with the following thicknesses: 4nm sSi and 145nm buried oxide. P-type transistors were then processed on top of such stacks and on regular SOI substrates (as references) with channels along the <110> directions. Gate length LG scaled down to 20nm were achieved after patterning. The Si and Si0.7Ge0.3/sSi thickness (HNW) under the HfSiON/TiN gate stack are around 10.5nm and 12.5nm respectively. For Si0.7Ge0.3/sSi transistors, the Si0.7Ge0.3 layer in the source/drain (S/D) regions was recessed down to the sSi etch-stop layer just after spacer etching. Then in-situ boron-doped Si0.7Ge0.3 raised S/Ds were used to thicken by 18nm and 25nm the access regions of the reference Si and the Si0.7Ge0.3/sSi devices, respectively. A second offset spacer was fabricated prior to S/D implantations, activation spike anneal and silicidation (NiPtSi silicide). Finally, tungsten contacts and standard Cu back-end-of-the-line process were used. Results. Long-channel hole mobility was extracted in Si0.7Ge0.3/sSi devices with NW widths varying from 10µm down to 20nm. As compared to SOI references, a higher hole mobility is observed for wide devices (W=10µm) but a lower hole mobility is obtained when reducing W to 20nm. Indeed, for wide devices, the biaxial compressive strain removes the degeneracy of the valence band and modifies the band structure in a manner that reduces the hole effective mass. On the contrary, the tensile strain raises in the narrowest devices the heavy hole subbands, which degrades mobility. At short LG, the strain induced by the cSiGe channels epitaxied on sSOI, the SiGe:B S/D and the CESL is analyzed and characterized. The top part of Fig. 1 shows a cross-sectional TEM image of a Si0.7Ge0.3/sSi device. The strain has been investigated using the geometric phase analysis (GPA) of high-angle annular dark-field images (HAADF). The strain distribution map is extracted with high resolution scanning transmission electron microscopy (STEM) along the S-D direction. As expected, a compressive strain is induced close to the Si0.7Ge0.3:B S-Ds (green color in Fig. 1). This results in enhanced short-channel performances. The tensile strain of sSOI substrate is then compensated and the saturation current definitely improved compared to SOI references for the same 0.9V over drive gate voltage (Fig. 2). Obviously the cSiGe channel also reduces the VTH and contributes to improved performances at VDD[9]. Finally, the electrical properties of Ω-gate Si0.7Ge0.3/sSi NW p-FETs are systematically examined for a wide range of NW widths (20nm<W<10µm) and gate lengths (20nm<LG<10µm). We show that the tensile strain can be compensated by Si0.7Ge0.3:B S-Ds at short gate length. A higher Ge concentration in the channel will allow to further improve p-FET performances on strained-SOI substrates.

BSIM4 parameter extraction for tri-gate Si nanowire transistors

We investigated the BSIM4 parameter extraction procedure for tri-gate Si nanowire transistors with different geometries and fabrication processes. SPICE modeling tool was used to extract the parameter from Id–Vg to Id–Vd characteristics with liner and saturation region. Dependence of source/drain parasitic resistances on nanowire width and gate sidewall thickness can be observed on the extracted parameters. Furthermore, parasitic capacitance was extracted from three-dimensional TCAD simulation with our fabricated device structure. Single sets of parameters can reproduce I–V characteristics with Lg down to 35nm for n-channel nanowire transistors. It was found that the extracted parameters will be a useful tool for characterizing the circuit performance of nanowire transistor. Therefore, this procedure is applicable to extract the BSIM4 model parameters for NW Tr. as well as other multi-gate FETs.

Comparison of Si < 100 > and < 110 > crystal orientation nanowire transistor reliability using Poisson–Schrödinger and classical simulations

In this paper we perform trap sensitivity simulation analysis of square nanowire transistors (NWT), comparing Poisson–Schrödinger (PS) and classical solutions. Both approaches result in a very different electrostatic behaviour due to strong quantum confinement effects in ultra-scaled NWTs such as the Si NWTs presented in this work. Statistical distributions of traps are investigated, modelling the steady state impact of Random Telegraph Noise and Bias Temperature Instabilities for two crystal orientations. Statistical simulations are performed to evaluate the reliability impact on threshold voltage and ON current, emphasising the importance of both confinement and trap distribution details for the proper assessment of reliability in nanowire transistors.

Influence of anharmonic phonon decay on self-heating in Si nanowire transistors

Anharmonic phonon-phonon scattering is incorporated into an electro-thermal quantum transport approach based on the nonequilibrium Green's function formalism. Electron-phonon and phonon-phonon interactions are taken into account through scattering self-energies solved in the self-consistent Born approximation. While studying self-heating effects in ultra-scaled Si nanowire transistors, it is found that the phonon decay process softens the artificial accumulation of high energy phonons caused by electron relaxations close to the drain region. This leads to an increase of the device current in the ON-state and a reduction of the effective lattice temperature.

A Comparative Study of Si, Ge and GaAs Cylindrical Nanowire Transistors with Non Equilibrium Greens Function Approach

A Comparative Study of Si, Ge and GaAs Cylindrical Nanowire Transistors with Non Equilibrium Greens Function Approach

Performance Benchmarking of 32 nm Predictive Technology Model CMOS with Silicon Nanowire Physic-Based Compact Model of Field-Effect Transistors for Digital Logic Applications

New variation of nanostructures are introduced and developed to sustain Moore's Law as device dimension is scaled drastically. Among those low dimensional technological innovation is silicon (Si) nanowire field-effect transistor (NWFET). The usefulness of Si NWFET is its compatibility with existing complementary metal-oxide semiconductor (CMOS) technology that been widely pursued for more than four decades. Device simulation of nanowire is essential to explore physics in depth and to assess, quantify and benchmark the device performance metrics with a nanoscale metal-oxide semiconductor field-effect transistor (MOSFET). SPICE model of Si NWFET is constructed based on the device model proposed by researchers from Purdue University. A semi-empirical solution of the self-consistent is presented so that the device model is made portable and can be simulated in SPICE and other platform. Then, silicon-based digital logic circuit namely inverter, NOR and NAND are simulated and analysed. The circuit performances of nanowire digital gates are then compared against 32 nm MOSFET in terms of energy-delay product, power-delay product, propagation delay and average power dissipation. The results shown that silicon nanowires perform better than 32 nm MOSFET generally due to the high velocity transport of quasi ballistic carriers and superior gate control.

Multiplex electrical detection of avian influenza and human immunodeficiency virus with an underlap-embedded silicon nanowire field-effect transistor

The label-free electrical detection of the binding of antibodies and antigens of avian influenza (AI) and human immunodeficiency (HIV) viruses is demonstrated through an underlap-embedded silicon (Si) nanowire field-effect transistor. The proposed sensor was fabricated on a silicon bulk wafer by a top-down process. Specifically, a Si nanowire was fabricated by a combined isotropic and anisotropic patterning technique, which is one route plasma etching process. The sensor was fabricated by a self-aligned process to the gate with tilted implantation, and it allows precise control of the underlap region. This was problematic in earlier underlap field-effect transistors fabricated by a conventional gate-last process. As a sensing metric to detect the binding of a targeted antibody, the transfer characteristic change was traced. Before and after differences between the antibody binding results were caused by changes in the channel potential on the underlap region due to the charge effect arising from the biomolecules; this is also supported by a simulation. Furthermore, the multiplex detection of AI and HIV is demonstrated, showing distinctive selectivity in each case. Thus, the proposed device has inherent benefits for the label-free, electrical, and multiplex detection of biomolecules. Moreover, its processes are compatible with commercialized technology presently used to fabricate semiconductor devices. This advantage is attractive for those involved in the construction of a point-of-care testing (POCT) system on a chip involving simple, low-cost and low-risk fabrication processes of novel structures and materials.