Si Nanowire Transistors Research Articles

Dopants and roughness induced resonances in thin Si nanowire transistors: A self-consistent NEGF-poisson study

Non-Equilibrium Green Function simulations of the effect of discrete ionised dopants and surface roughness in Silicon nanowire transistors show the strong presence of resonances in the transmission coefficients. These resonances or quasi-bound states are the main component in the screening of dopants and play an important role in the current flow. Resonances appear through a self-consistent calculation of the electron density and potential. In this work we study several examples that exhibit different types of resonances. We start with a single impurity case and gradually evolved to a complex case with several random impurities. Interface roughness in a very narrow nanowire could induce resonant cavities as is proven in this paper. The effect of these resonances in the current-voltage characteristic of the transistors is considered in detail.

Spectroscopic charge pumping in Si nanowire transistors with a high-κ/metal gate

The density of interface states has been investigated experimentally on silicon nanowire transistors (SNWTs), with a high-k/metal gate stack. Low temperature measurements down to 25 K have been performed to determine the interface trap energy distribution throughout the Si band gap on nanowire devices. We have shown that SNWTs exhibit a higher trap density together with a modified energy profile as compared to conventional planar devices. Finally these spectroscopic measurements have been compared to electron mobility to complete the analysis and to further understand the impact of the interface on carrier transport.

Electron tomography of gate-all-around nanowire transistors

We present a study of gate-all-around (GAA) Si nanowire transistor structures using high angle annular dark field (HAADF) STEM tomography. Device structures have been prepared in needle shaped samples using a focused ion beam (FIB), in order to allow sample rotation to +/− 80°. Tomograms are presented, both from a full three channel device structure and also from a single wire test structure, without the hydrogen annealing step. It is observed that hydrogen annealing alters the rectangular cross section of the nanowires, narrowing them and smoothing the corners.

High-Performance Si Nanowire Transistors on Fully Si Bulk Substrate From Top-Down Approach: Simulation and Fabrication

A new method to fabricate high-performance gate-all-around silicon (Si) nanowire transistors (SNWTs) based on fully Si bulk (FSB) substrate is proposed and demonstrated by both simulation and experiments in this paper. Due to the large fan-out and deep junction of Si source/drain (S/D) region connecting with the bulk substrate, the FSB SNWTs can effectively alleviate the self-heating effects with technology scaling. Thermal behavior of multiwire SNWTs is investigated and FSB SNWTs show superior self-heating immunity to SNWTs based on Si-on-insulator (SOI) substrate (SOI SNWTs). In addition, the bottom parasitic transistor can be well suppressed in this structure. Although FSB SNWTs have larger gate parasitic capacitance, the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CV</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> is found to be comparable to the SOI SNWTs. With self-aligned, fully epi-free compatible CMOS processes, this new architecture was successfully fabricated, which exhibit high on-off current ratio of 2.6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> due to better heat dissipation and low S/D resistance realized in this structure.

3-D Nonequilibrium Green's Function Simulation of Nonperturbative Scattering From Discrete Dopants in the Source and Drain of a Silicon Nanowire Transistor

As these As transistors are scaled to nanometer dimensions, the discreteness of the dopants becomes increasingly important. Transistors of 3 times 3 nm2 cross section contain, on average, approximately one dopant atom per nanometer of length, making any self-averaging impossible. The individual random dopants act as localized scatterers whose distribution, and therefore, impact on the electron transport, varies from device to device. This is complemented by electrostatic variation in the potential that controls the threshold voltage and the dominant current paths. The current density is greatly influenced by resonances associated with the attractive potential of the donors and screening effects. In this paper, for the first time, a full 3-D nonequilibrium Green's function (NEGF) simulation in the effective mass approximation has been used to study the influence of individual discrete donors in the source/drain on the I-V characteristics of a narrow n-channel Si nanowire transistor. We have compared devices with microscopically different configuration of dopants. The simulated variations in the I-V curves are analyzed with reference to the behavior of the transmission coefficients. We have highlighted the importance of resonance states when solving the NEGF and Poisson equations self-consistently.

Current Variability in Si Nanowire MOSFETs Due to Random Dopants in the Source/Drain Regions: A Fully 3-D NEGF Simulation Study

In this paper, we study the impact of random discrete dopants in the source/drain (S/D) leads on the current variability of a gate-all-around Si nanowire transistor. Due to the strong inhomogeneities of the self-consistent electrostatic potential, a <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fully</i> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3D</i> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">real-space</i> nonequilibrium Green's function (NEGF) formalism is used. N-channel transistors with random discrete donors in the S/D regions varying in both numbers and locations have been simulated. We have studied the impact of quasi-bound (QB) states and transmission resonances associated with the attractive potential of the donors on the screening of the impurities and on the current transport. The convergence of the coupled 3D Poisson-NEGF equations for narrow wires with discrete dopants is cumbersome due to the quasi-discrete nature of QB states and resonances of the attractive impurity potential. We present a robust solution strategy dealing with the convergence challenges. Large variations in the on-current and modest variations in the subthreshold slope are observed in the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> characteristics when comparing devices with microscopically different discrete dopant configurations. We have also estimated the access resistance associated with the random dopant regions in the source and the drain leads and find very good agreement with the resistance estimated from the bulk silicon mobility at the same doping concentration.

Quantum Transport Simulation of Silicon-Nanowire Transistors Based on Direct Solution Approach of the Wigner Transport Equation

In this paper, we present a self-consistent and 3D quantum simulator for Si-nanowire transistors based on the Wigner function model and multidimensional Schrodinger-Poisson algorithm. To achieve a sufficient numerical accuracy for calculating subthreshold current, we introduced a third-order differencing scheme for discretizing the drift term in the Wigner transport equation. By comparing with semiclassical Boltzmann and nonequilibrium Green's function approaches, the validity of the present simulator is confirmed. We also demonstrate that the source-drain tunneling is a critical physical phenomenon related to a scaling limit of nanowire devices, and the semiclassical simulation measurably underestimates a minimum gate length.

Nickel Salicided Source/Drain Extensions for Performance Improvement in Ultrascaled (Sub 10 nm) Si-Nanowire Transistors

This letter demonstrates successful integration of Gate-All-Around (GAA) nanowire (NW) transistors with low-resistivity metallic NW point contacts at source/drain extensions. Ultrascaled GAA silicon NW transistors with gate lengths down to 8 nm have been achieved, exhibiting good performance among the NW FETs reported to date. Compared to the reference devices, the metallic contact NW devices show 580% enhancement in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> from 103 to 705 muA/mum , at a fixed <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> of 10 nA/mum . Nickel silicide resistivity for ultrathin films is also investigated in this letter for the integration of salicided source/drain extensions with the GAA NW process. Experimental results show that 4 nm of deposited Ni is suitable for forming NW contacts with 10-nm diameters, which is thin enough to avoid oversilicidation while meeting the low-resistivity requirements.

Experimental Investigations on Carrier Transport in Si Nanowire Transistors: Ballistic Efficiency and Apparent Mobility

As devices continue scaling down into nanometer regime, carrier transport becomes critically important. In this paper, experimental studies on the carrier transport in gate-all-around (GAA) silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top-down approach. Both ballistic efficiency and apparent mobility were characterized. A modified experimental extraction methodology for SNWTs is adopted, which takes into account the impact of temperature dependence of parasitic source resistance in SNWTs. The highest ballistic efficiency at room temperature is observed in sub-40-nm n-channel SNWTs due to their quasi-1-D carrier transport. The apparent mobility of GAA SNWTs are also extracted, showing their close proximity to the ballistic limit as shrinking the gate length, which can be explained by Shur's model. The physical understanding of the apparent mobility in SNWTs is also discussed using flux's scattering matrix method.

Stability of HSQ nanolines defined by e-beam lithography for Si nanowire field effect transistors

Multiple instability states, e.g., grouped collapse, single collapse, wavy, and grouped wavy states, have been observed in hydrogen silses quioxane (HSQ) nanolines defined by electron beam lithography (EBL). Experimental data show that the critical aspect ratio of the HSQ lines dramatically increase when the line pitch reduced to sub-100-nm, which is opposite to theoretical models for capillary forces and swelling strain. Such contradiction can be well explained only if Young’s modulus is considered as a significantly varying factor. Further, experimental data show a dramatic decrease in swelling strain and increase in oxygen contents in HSQ with increasing EBL dose, indicating that it is the change in Young’s modulus rather than the capillary force or swelling strain that dominates the instability behaviors at the nanoscale. Stable high aspect ratio HSQ nanolines over metal pads were used to make working Si nanowire transistors on Si on insulator substrates. 12–14nm HSQ lines with aspect ratios of 11–14 have been obtained. Fabricated field effect transistors using back-gate configuration has shown expected performance towards biosensing applications.

Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach

We present the monolithic integration of gate-all-around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. Inverters are chosen as the test vehicles for demonstration. Empirically optimized designs show sharp ON–OFF transitions with high voltage-gains (e.g., ΔVOUT/ΔVIN up to ∼45) and symmetric pull-up and pull-down characteristics. The matching of the drive currents of n- and p-MOSFETs is achieved using different number of nanowire channels for N- and P-MOS transistors. The inverter maintains its good transfer characteristics and noise margins for wide range of VDD tested down to 0.2V. The detailed experimental characterization is discussed along with the electrical characteristics of the individual transistors comprising the inverter. The performances of the inverters are discussed vis-à-vis those reported in the literature using advanced non-classical device architectures such as FinFETs. The integration potential of GAA Si-nanowire transistors to realize CMOS circuit functionality using top-down approach is thus demonstrated.

CMOS Inverter Based on Gate-All-Around Silicon-Nanowire MOSFETs Fabricated Using Top-Down Approach

This letter demonstrates, for the first time, the integration of gate-all-around (GAA) Si-nanowire transistors into CMOS inverters using top-down approach. With matching of the drive currents of n- and p-MOSFETs using different gate lengths to achieve symmetric pull-up and pull-down, sharp ON- OFF transitions with high voltage gains (e.g., Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> /Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IN</sub> up to ~ 40 for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1.2 V) are obtained. The inverter maintains its good transfer characteristics and noise margins for wide range of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> tested down to 0.4 V. Individual transistors show excellent subthreshold characteristics and drive currents. The results are discussed in light of the circuit performances reported for other advanced nonclassical device architectures such as FinFETs. The integration potential of GAA Si-nanowire transistors to realize CMOS-circuit functionality is thus demonstrated.

Fabrication of Poly-Silicon Nano-Wire Transistors on Plastic Substrates

We report the fabrication and characterization of poly-Si nanowire transistors on flexible substrates. The nanowire transistors are fabricated on a SiO2/Si substrate using conventional CMOS processes, and then they are transferred onto polyimide substrates. The transfer process is performed by spin-coating of polyimide, curing (annealing) of the polyimide layer, and removal of the SiO2 sacrificial layer. The optimized curing condition results in the maximum bending of 150 degrees with full recovery. The nanowire transistors exhibit transistor characteristics as a function of the backgate bias. Our new process can be applied to the fabrication of Si-nanowire transistors with larger mobilities.

Fabrication of Poly-Silicon Nano-Wire Transistors on Plastic Substrates

We report the fabrication and characterization of poly-Si nanowire transistors on flexible substrates. The nanowire transistors are fabricated on a SiO2/Si substrate using conventional CMOS processes, and then they are transferred onto polyimide substrates. The transfer process is performed by spin-coating of polyimide, curing (annealing) of the polyimide layer, and removal of the SiO2 sacrificial layer. The optimized curing condition results in the maximum bending of 150° with full recovery. The nanowire transistors exhibit transistor characteristics as a function of the backgate bias. Our new process can be applied to the fabrication of Si-nanowire transistors with larger mobilities.

A Self-Consistent Full 3-D Real-Space NEGF Simulator for Studying Nonperturbative Effects in Nano-MOSFETs

In this paper, we present a full 3-D real-space quantum-transport simulator based on the Green's function formalism developed to study nonperturbative effects in ballistic nanotransistors. The nonequilibrium Green function (NEGF) equations in the effective mass approximation are discretized using the control-volume approach and solved self-consistently with the Poisson equation in order to obtain the electron and current densities. An efficient recursive algorithm is used in order to avoid the computation of the full Green function matrix. This algorithm, and the parallelization scheme used for the energy cycle, allow us to compute very efficiently the current-voltage characteristic without the simplifying assumptions often used in other quantum-transport simulations. We have applied our simulator to study the effect of surface roughness and stray charge on the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> characteristic of a 6-nm Si-nanowire transistor. The results highlight the distinctly 3-D character of the electron transport, which cannot be accurately captured by using 1-D and 2-D NEGF simulations, or 3-D mode-space approximations.

Analog/RF Performance of Si Nanowire MOSFETs and the Impact of Process Variation

In this paper, the analog/RF performance of Si nanowire transistors (SNWTs) and the impact of process variation are investigated for the first time. Analog/RF figures of merit of SNWTs are studied, including transconductance efficiency gm/Id, intrinsic gain gm/gd, cutoff frequency ft , and maximum oscillation frequency fmax. The results indicate that SNWTs exhibit superior intrinsic RF scaling capability and are suitable for low-power analog/RF applications. The impact of nanowire cross-sectional shape fluctuation that is caused by process variation is studied and found to be relatively severe, and the acceptable variation tolerance for RF integrated circuit design is given

Atomistic treatment of interface roughness in Si nanowire transistors with different channel orientations

Nanowire transistors with a perfect crystal structure and a well-defined Si–SiO2 interface cannot be grown with the actual technology. The shape of the semiconducting channel varies from source to drain. By self-consistently coupling the three-dimensional Schrödinger and Poisson equations, interface roughness (IR) effects are studied in Si triple-gate nanowire transistors with [100], [110], [111], and [112] oriented channels. The full-band electronic transport is computed in the nearest-neighbor sp3d5s* tight-binding model. IR is included by adding or removing atoms at the Si surface. A comparison of the different channel orientations is achieved by calculating the variations of the transistor threshold voltage.

Complementary Symmetry Silicon Nanowire Logic: Power‐Efficient Inverters with Gain

Wired for high performance: The role of relative surface area in Si nanowire (NW) transistor (see image) performance was examined by comparing the performance of microwire (μW) field-effect transistors (FETs) fabricated side-by-side with NW FETs. Both n- and p-type NW FETs were found to be more sensitive to surface states than their μW counterparts; these results are utilized to produce NW n-FETs with consistent performance. Supporting information for this article is available on the WWW under http://www.wiley-vch.de/contents/jc_2296/2006/z600249_s.pdf or from the author. Please note: The publisher is not responsible for the content or functionality of any supporting information supplied by the authors. Any queries (other than missing content) should be directed to the corresponding author for the article.

Theoretical investigation of surface roughness scattering in silicon nanowire transistors

Using a full three-dimensional (3D), quantum transport simulator, we theoretically investigate the effects of surface roughness scattering (SRS) on the device characteristics of Si nanowire transistors (SNWTs). The microscopic structure of the Si/SiO2 interface roughness is directly treated by using a 3D finite element technique. The results show that (1) SRS reduces the electron density of states in the channel, which increases the SNWT threshold voltage, and (2) the SRS in SNWTs becomes less effective when fewer propagating modes are occupied, which implies that SRS is less important in small-diameter SNWTs with few modes conducting than in planar metal-oxide-semiconductor field-effect-transistors with many transverse modes occupied.

Detection of single charges and their generation-recombination dynamics in Si nanowires at room temperature

Detection of single electrons and single holes is demonstrated at room temperature in Si nanowire transistors using an electron-hole (e–h) system. Photogenerated carriers are stored in a quantum dot electrically formed in a Si wire by a front gate. The stored charges affect the current of the other type of carriers that flow along the bottom of the Si wire. The linear photoresponce of single-charge generation is observed. It is revealed that the recombination occurs by a bimolecular process, suggesting that it is due to the e–h interband transition. These results open up the possibility of developing single-photon devices with this system.