High-Performance Si Nanowire Transistors on Fully Si Bulk Substrate From Top-Down Approach: Simulation and Fabrication

Abstract

A new method to fabricate high-performance gate-all-around silicon (Si) nanowire transistors (SNWTs) based on fully Si bulk (FSB) substrate is proposed and demonstrated by both simulation and experiments in this paper. Due to the large fan-out and deep junction of Si source/drain (S/D) region connecting with the bulk substrate, the FSB SNWTs can effectively alleviate the self-heating effects with technology scaling. Thermal behavior of multiwire SNWTs is investigated and FSB SNWTs show superior self-heating immunity to SNWTs based on Si-on-insulator (SOI) substrate (SOI SNWTs). In addition, the bottom parasitic transistor can be well suppressed in this structure. Although FSB SNWTs have larger gate parasitic capacitance, the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CV</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> is found to be comparable to the SOI SNWTs. With self-aligned, fully epi-free compatible CMOS processes, this new architecture was successfully fabricated, which exhibit high on-off current ratio of 2.6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> due to better heat dissipation and low S/D resistance realized in this structure.