Abstract

In this paper we perform trap sensitivity simulation analysis of square nanowire transistors (NWT), comparing Poisson–Schrödinger (PS) and classical solutions. Both approaches result in a very different electrostatic behaviour due to strong quantum confinement effects in ultra-scaled NWTs such as the Si NWTs presented in this work. Statistical distributions of traps are investigated, modelling the steady state impact of Random Telegraph Noise and Bias Temperature Instabilities for two crystal orientations. Statistical simulations are performed to evaluate the reliability impact on threshold voltage and ON current, emphasising the importance of both confinement and trap distribution details for the proper assessment of reliability in nanowire transistors.

Highlights

  • Aggressive downscaling of transistors in advanced CMOS technologies has reached dimensions at which the discreteness of charge and matter has to be carefully considered

  • Statistical variations due to single atom properties and positions in the critical regions of the transistors have to be taken into account to understand the significant increase in the dispersion of parameters of ultra-scaled transistors [1,2,3]. This led to the introduction of new transistor architectures such as FDSOI, FinFET, and nano-wire transistors, offering a better electrostatic control of the channel by the gate and allowing the reduction of channel doping, which is the dominant source of statistical variability [1,2,4]

  • In order to investigate the impact of the crystal orientation on steady-state Random Telegraph Noise (RTN) and Bias Temperature Instabilities (BTI) effects, we have generated a sample of hundred randomly distributed interface traps; the probability of having a trap on the side interfaces in the b110N channel orientation is twice more probable compared to the b 100 N channel orientation, following measurement results and this effect enhances the quantum confinement differences between these two crystal orientations

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Summary

Introduction

Aggressive downscaling of transistors in advanced CMOS technologies has reached dimensions at which the discreteness of charge and matter has to be carefully considered. Statistical variations due to single atom properties and positions in the critical regions of the transistors have to be taken into account to understand the significant increase in the dispersion of parameters of ultra-scaled transistors [1,2,3]. This led to the introduction of new transistor architectures such as FDSOI, FinFET, and nano-wire transistors, offering a better electrostatic control of the channel by the gate and allowing the reduction of channel doping, which is the dominant source of statistical variability [1,2,4]. In addition atomic density, dangling bond density, and roughness are different and traps are more likely to be created at the crystal planes perpendicular to the b110N direction [5,6]

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