Si Nano Research Articles

J2230104 集積化結合シリコンナノ振動子

J2230104 集積化結合シリコンナノ振動子

Structural and Luminescence Properties of SiGe Nanostructures with Ge Quantum Dots

A study of technological parameters of growing of SiGe like number of Ge nano layers, layers thickness and temperature of substrate are reported. These parameters play an important role in the optical properties of SiGe nanostructures with Ge quantum dots. A long lifetime of radiative recombination for band-to-band transition is attributed to indirect band in Si. As a consequence, the dominant recombination at deep level defects is non- radiative. In order to enhance the intensity of luminescence band at 0.8 eV that related to radiative recombination of Ge quantum dots, the hydrogen plasma ion treatment of SiGe nanostructure were utilized. Improving of the luminescence intensity is an important parameter to increase the quantum efficiency of optoelectronic devices based on the Si nano layer with Ge quantum dots.

양산용 80 kW급 RF Plasma Torch System 개발 및 Si 나노분말 제조 공정 연구

80 kW RF 플라즈마 토치 시스템을 개발하기 위하여, 토치 시스템에 대한 온도, 유체 거동 분석 등의 보다 많은 정보의 추출을 위하여 3차원 시뮬레이션을 진행했다. 파우더 주입관 위치, 입력 전류 변화에 따른 플라즈마 생성 특성, 세라믹 원통관 길이에 따른 플라즈마 방전 특성, 및 공정가스 유량에 따른 플라즈마 온도특성 등을 시뮬레이션 했다. 시뮬레이션을 통해 설계 제작된 RF 열 플라즈마 토치의 경우, 최대 89.3 kW까지 파워 인가가 측정되었다. 개발된 80 kW급 RF 열 플라즈마 토치 시스템의 양산성 평가로 Si 나노분말을 제조하고 특성을 고찰하였다. Si 나노분말의 생산량이 평균 539 g/hr의 양산 수준과 71.6%의 높은 수율을 달성했으며, 제조된 나노 분말은 <TEX>$D_{99}/D_{50}$</TEX>가 1.98의 좋은 입경 균일 분포도를 나타내었다. In order to develop of 80 kW RF plasma torch system, we achieved three-dimensional simulations for the extraction of more information as temperature in torch and fluid behavior analysis, etc. The position of powder injection tube, the plasma discharge characteristics with various input current and various length of ceramic tube, and the plasma temperature characteristics with process gas flow rate such those was simulated. RF thermal plasma torch designed by simulation was manufactured that was measured to the maximum of 89.3 kW power. The mass production using developed 80 kW RF thermal plasma torch system were investigated by characteristics manufactured of Si nano powder. The mass-production level of Si nano-powder was average of 539 g/hr and high yield rate of 71.6%, respectively. The particle size distribution <TEX>$D_{99}/D_{50}$</TEX> of manufacturing nano-powder was investigated to 1.98 as a good uniform.

自己集積化ナノリソグラフィを利用したSiナノホールアレイ形成とCu埋め込み

自己集積化ナノリソグラフィを利用したSiナノホールアレイ形成とCu埋め込み

Minimizing reflection losses from metallic electrodes and enhancing photovoltaic performance using the Si-micrograting solar cell with vertical sidewall electrodes

Researchers have focused on the development of Si nano- or micro-structured solar cells (SCs) because of their enhanced optical absorption properties and their ability to decouple minority carrier diffusion and light absorption paths. We adopt a low-cost method to monolithically fabricate Si-micrograting SC (SiMG-SC) with vertical sidewall electrodes and a vertical multi-junction, which minimizes the reflection losses from conventional planar metallic electrodes and increases the minority carrier collection probability. We consequently intensified the photovoltaic properties, i.e., the current density, fill factor, and power conversion efficiency, by 11.2%, 23.7%, and 52.9%, respectively, compared to those of the control SCs.

Strength enhancement of nano patterns from edge lithography for nanoimprint mold

► SiO 2 nano patterns are fabricated by edge lithography. ► Nano pattern strength is enhanced by small Si step. ► Nano patterns are transferred by thermal nano imprint. ► Polystyrene nano patterns are obtained. ► Si nano trench is successfully fabricated. Although SiO 2 nano-patterns with a high aspect ratio could already be fabricated by edge lithography, the SiO 2 nano-patterns were often not suitable as molds for nano-imprint lithography because they were too fragile. To improve the SiO 2 nano-pattern strength, a small Si step was fabricated around the bottom of the SiO 2 nano-patterns. Such strength enhanced SiO 2 nano-patterns were successfully replicated into both polymethylmethacrylate and polystyrene films on a Si substrate by thermal nano-imprint lithography. Resist patterns 25 nm in width and 430 nm in depth were obtained. The residual layer was removed in an N 2 /O 2 plasma. Si trenches were fabricated using the imprinted polystyrene nano-patterns, and Si nano-trenches 35 nm in width and 285 nm in depth were thereby successfully obtained.

Embedded Si Nano Wire Anode for Lithium-Ion Secondary Cells

not Available.

Diameter-Reduced Islands for Nanofabrication Toward Bit Patterned Magnetic Media

Thin films deposited on a flat substrate, if the adhesion is not strong, can be made to ball up and form discrete islands upon heating to elevated temperatures due to the surface energy difference. We have applied this useful process to electron beam lithography (EBL) and nano-imprinting lithography (NIL). By combining the ball-up processes of Ni thin film with e-beam lithography followed by reactive ion etching, Si nano islands and vertical nanopillars as small as 10 nm in diameter have been realized. There is a strong correlation between the initial thickness of Ni mask layer and final Ni island diameter obtained after ball-up. The smallest island diameter is obtained using ~ 5-nm initial Ni layer thickness. Below 3-nm initial layer thickness, the intended ball-up reaction does not occur. With more than ~ 15-nm initial metal film thickness, the Ni layer is broken up into nonspherical and highly irregular structures. [Co/Pd] <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> multilayer magnetic thin films deposited on prepatterned substrate by nano imprinting lithography with versus without island ball-up process have been investigated for bit patterned media studies. The coercivity of magnetic islands can be enhanced by island diameter reduction using the ball up process.

Serial and Parallel Si, Ge, and SiGe Direct-Write with Scanning Probes and Conducting Stamps

Precise materials integration in nanostructures is fundamental for future electronic and photonic devices. We demonstrate Si, Ge, and SiGe nanostructure direct-write with deterministic size, geometry, and placement control. The biased probe of an atomic force microscope (AFM) reacts diphenylsilane or diphenylgermane to direct-write carbon-free Si, Ge, and SiGe nano and heterostructures. Parallel direct-write is available on large areas by substituting the AFM probe with conducting microstructured stamps. This facile strategy can be easily expanded to a broad variety of semiconductor materials through precursor selection.

Effects of Thickness on Cycleability of Si Nano Platelet Anodes in Lithium-Ion Cells

not Available.

Broadband and wide-angle antireflection subwavelength structures of Si by inductively coupled plasma etching using dewetted nanopatterns of Au thin films as masks

We report the broadband and wide-angle antireflection subwavelength structures (SWSs) on silicon (Si) substrate by inductively coupled plasma (ICP) etching using gold (Au) nanopatterns as etch masks. The reflectance depends strongly on the etched profile of Si SWSs which is influenced by both thermal dewetting and etching conditions. The size, shape, and array geometry of nano-sized patterns, which are produced via the thermal dewetting of Au thin films, are optimized under proper heat treatment. The etched depth and shape of Si nano tips are controlled additionally by ICP power, thus achieving the efficient antireflection characteristics. The optimized Si SWS with the tapered structure and sharp tips at high ICP power leads to a significantly low reflectance value of <1% at wavelengths of 350–1100nm. Furthermore, it exhibits a wide-angle antireflection property of <7.5% at incident angles of 8–70° over a wide wavelength range of 300–1100nm.

Fabrication of Nanometer Sized Si Dot Arrays Using Ar Ion Milling with Calixarene Resist Dot Arrays

In this study, we investigated the possibility of forming the fine Si dot arrays by means of electron beam (EB) lithography and dry etching technique for the future’s devices with nano-scale structures. We examined the properties of Ar ion milling for the fabrication of nanometer sized Si dot arrays on a Si substrate. We have succeeded in forming 40 nm pitched Si dot arrays with a diameter of &lt;20 nm using dot array patterns of the calixarene resist as a mask. We also obtained the Ar ion milling property that there exists the horizontal milling rate as well as the vertical milling rate. We formed Si dot arrays with a dot diameter of about 10 nm using this property. It was clarified that Ar ion milling and EB lithography with calixarene resist has the potential to form Si nano dot arrays for the nano devices.

Back Cover: Phys. Status Solidi RRL 1–2/2010

physica status solidi (RRL) – Rapid Research LettersVolume 4, Issue 1-2 Back Cover Back Cover: Phys. Status Solidi RRL 1–2/2010 First published: 04 February 2010 https://doi.org/10.1002/pssr.201090001AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Graphical Abstract Silicon can intercalate about 10 times more Li that the standard graphite anode presently used in Li ion batteries. Thus it would be a very desirable material for high capacity batteries. The large volume expansion encountered upon Li incorporation into Si will fracture bulk Si but not Si nano¬wires. In their Rapid Research Letter on p. 4, H. Föll et al. address the fabrication of Si nanowire arrays with optimized geometry via electrochemical pore etching in Si followed by isotropic chemical etching until the pore walls coalesce and nanowire arrays remain. Galvanically deposited Cu provides the electrical connection and protects the remaining bulk Si. First test batteries made with such Si nanowires anodes not only demostrated the expected high capacity but also showed virtually no capacity losses for more than 60 charge/discharge cycles. Volume4, Issue1-2February 2010 RelatedInformation

쇼트키 장벽 관통 트랜지스터 구조를 적용한 실리콘 나노점 부유 게이트 비휘발성 메모리 특성

쇼트키 장벽 관통 트랜지스터에 실리콘 나노점을 부유 게이트로 사용하는 비휘발성 메모리 소자를 제작하였다. 소스/드레인 영역에 어븀 실리사이드를 형성하여 쇼트키 장벽을 생성하였으며, 디지털 가스 주입의 저압 화학 기상 증착법으로 실리콘 나노점을 형성하여 부유 게이트로 이용하였다. 쇼트키 장벽 관통 트랜지스터의 동작 상태를 확인하였으며, 게이트 전압의 크기 및 걸어준 시간에 따른 트랜지스터의 문턱전압의 이동을 관찰함으로써 비휘발성 메모리 특성을 측정하였다. 초기 <TEX>${\pm}20\;V$</TEX>의 쓰기/지우기 동작에 따른 메모리 창의 크기는 <TEX>${\sim}5\;V$</TEX> 이었으며, 나노점에 충분한 전하 충전을 위한 동작 시간은 10/50 msec 이었다. 그러나 메모리 창의 크기는 일정 시간이 지난 후에 0.4 V로 감소하였다. 이러한 메모리 창의 감소 원인을 어븀 확산에 따른 결과로 설명하였다. 본 메모리 소자는 비교적 안정한 쓰기/지우기 내구성을 보여주었으나, 지속적인 쓰기/지우기 동작에 따라 수 V의 문턱전압 이동과 메모리 창의 감소를 보여주었다. 본 실험 결과를 가지고 실리콘 나노점 부유게이트가 쇼트키 장벽 트랜지스터 구조에 접목 가능하여 초미세 비휘발성 메모리 소자로 개발 가능함을 확인하였다. We fabricated a Si nano floating gate memory with Schottky barrier tunneling transistor structure. The device was consisted of Schottky barriers of Er-silicide at source/drain and Si nanoclusters in the gate stack formed by LPCVD-digital gas feeding method. Transistor operations due to the Schottky barrier tunneling were observed under small gate bias < 2V. The nonvolatile memory properties were investigated by measuring the threshold voltage shift along the gate bias voltage and time. We obtained the 10/50 mseconds for write/erase times and the memory window of <TEX>$\sim5V$</TEX> under <TEX>${\pm}20\;V$</TEX> write/erase voltages. However, the memory window decreased to 0.4V after 104seconds, which was attributed to the Er-related defects in the tunneling oxide layer. Good write/erase endurance was maintained until <TEX>$10^3$</TEX> write/erase times. However, the threshold voltages moved upward, and the memory window became small after more write/erase operations. Defects in the LPCVD control oxide were discussed for the endurance results. The experimental results point to the possibility of a Si nano floating gate memory with Schottky barrier tunneling transistor structure for Si nanoscale nonvolatile memory device.

Study of Self-Heating Phenomena in Si Nano Wire MOS Transistor

In this study, I have numerically investigated the temperature distribution of n-type Si Nano Wire MOS Transistor induced by the self-heating effect by using a 3-D device simulator. The dependencies of temperature distribution within the Si Nano Wire MOS Transistor on both its gate length and width of the Si nano wire were analyzed. First, it is shown that the peak temperature in Si Nano Wire MOS Transistor increases by 100K with scaling the gate length from 54nm to 14nm in the case of a 50nm width Si nano wire. Next, it is found that the increase of its peak temperature due to scaling the gate length can be suppressed by scaling the size of the Si nano wire, for the first time. The peak temperature suppresses by 160K with scaling the Si nano wire width from 50nm to 10nm in the case of a gate length of 14nm. Furthermore, the heat dissipation in the gate, drain, and source direction are analyzed, and the analytical theory of the suppression of the temperature inside Si Nano Wire MOSFET is proposed. This study shows very useful results for future Si Nano Wire MOS Transistor design for suppressing the self-heating effect.

THE DEPOSITION AND CONTROL OF SELF ASSEMBLED SILICON NANO ISLANDS ON CRYSTALLINE SILICON

The formation of nano sized Si structures during the annealing of silicon rich oxide (SRO) films was investigated. These films were synthesized by low pressure chemical vapor deposition (LPCVD) and used as precursors, a post-deposition thermal annealing leads to the formation of Si nano crystals in the SiO 2 matrix and Si nano islands ( Si nI ) at c-Si /SRO interface. The influences of the excess Si concentration, the incorporation of N in the SRO precursors, and the presence of a Si concentration gradient on the Si nI formation were studied. Additionally the influence of pre-deposition substrate surface treatments on the island formation was investigated. Therefore, the substrate surface was mechanical scratched, producing high density of net-like scratches on the surface. Scanning electron microscopy (SEM) and high resolution transmission electron microscopy (HRTEM) were used to characterize the synthesized nano islands. Results show that above mentioned parameters have significant influences on the Si nIs . High density nanosized Si islands can epitaxially grow from the c-Si substrate. The reported method is very simple and completely compatible with Si integrated circuit technology.

Formation of Si Nanocrystals in SiOx Films Induced by Thermal Plasma Jet Annealing and Its Application to Floating Gate Memory

Polycrystalline Si (poly-Si) thin film transistors (TFTs) have been utilized for logic and analog circuits in display applications. For further improvement in functionality, non-volatile memory operation of TFT has been anticipated. In MOSFET applications, Si nanocrystals embedded in SiO2 matrix are used as charging nodes in floating gate memory devices. Si nanocrystals are advantageous in terms of better retention characteristics compared to poly-Si floating gate because charged dots are electrically separated each other and charge escape via SiO2 defects are suppressed to a small number. Recently, good performance of low-temperature processed TFT memory using Si nano crystals formed by plasma enhanced chemical vapor deposition (PECVD) has been reported.

Silicon nanodot arrays patterned using diblock copolymer templates

Dense and periodic arrays of holes and Si nano dots were fabricated on silicon substrate. The holes were approximately 20–40 nm wide, 40 nm deep and 40–80 nm apart. To obtain nano-size patterns, self-assembling resists were used to produce layer of hexagonally ordered parallel cylinders of polymethylmethacrylate (PMMA) in polystyrene (PS) matrix. The PMMA cylinders were degraded and removed with acetic acid rinse to produce a PS. 10 nm-thick Au thin film was deposited by using electron beam evaporator. PS template was removed by lift-off process. Arrays of Au nano dot were transferred by using fluorine-based reactive ion etching. Au nano dots were removed by sulfuric acid. Si nano dots size and height were 24–70 nm and 20–30 nm respectively. Sequential oxidation-wet etching method reduced size of Si nano dots. Reduced sized silicon nano dots diameter and height were 18 nm and 12 nm, respectively. Nanopatterned holes sizes were observed by field emission scanning electron microscope (FESEM) and atomic force microscopy.

Mechanism of Self-Heating Phenomena in Si Nano Wire MOS Transistor

Mechanism of Self-Heating Phenomena in Si Nano Wire MOS Transistor

Study of Self-Heating in Si Nano Structure for Floating Body-Surround Gate Transistor with High-k Dielectric Films

In this study, to overcome temperature-related problems of floating body-surround gate transistors with high-k materials, we have numerically investigated the temperature distribution in n-type silicon (Si) nanowires, in relation to the self-heating effect at steady state, by using a three-dimensional (3-D) device simulator. The dependences of temperature distribution in the Si nanowire on impurity concentration and cross sectional area were analyzed. First, it was found that the maximum temperature in the Si nanowire increases with increasing impurity concentration, and the increasing maximum temperature leads to a larger shift of the position of the maximum temperature from the center. Next, it was also found that the temperature distribution is independent of the cross sectional area of the Si nanowire. Finally, it was clarified that the asymmetric temperature distribution in the Si nanowire is caused by the Seebeck effect. This study shows useful results for future nano-scale silicon–metal oxide semiconductor (Si–MOS) device design to suppress the self-heating effect.